EXAMS 2023 CO and Architecture

Question

A RISC machine has a clock period of 50ns. 20% of its commands are LOAD and STORE commands. On average, 50% NO-OP instructions and 50% useful instructions are placed in the delay slots of these instructions. In the new model of the machine that is released on the market, the period has been reduced to 45ns. However, the cost of this reduction is that two more delay slots are needed for each memory instruction, and only 20% of all delay slots are filled with useful instructions. Which machine is faster and by how much?

Comments

What is the answer to this one? I tried but not sure whether I am right or not.

Answer 1

Question does not include the number of delay slots..
lets say in Machine 1 [M1], delay slots = x.

 

$ET_1 = [1+0.2*0.5*x]*50 = [1+0.01*x]*50 $

$ET_2 = [1+0.2*0.8*(x+2)]*45 = [1+0.16*(x+2)]*45$

 for x = 1

$ET_1 = 1.01 * 50 = 50 ns$

$ET_2 = 1.48 * 45 = 66.6 ns$
 

Machine 1 is faster. But, it should be mentioned what is the original number of delay slots.

Comments

How did you get the formula? Can you tell the chapter for this sum?

---

There’s no formula @Rohit Chakraborty It is from pipelining with delayed branching technique to reduce control hazards. You just use your concept and visualize the pipeline. and hope the answer would be right.
(I think that is why pipeline is tough. Simple formulas would be so much better).


 

---

Yeah...You’re right….But there’s one more question….I’ve forgotten the concepts on the basis of which you’ve calculated the branch frequency(0.2 X 0.5)...Can you plz explain why you’ve taken that

---

In ET1: 0.2*0.5=0.1