Consider the classical 5-stage pipeline MIPS processor. Assume the individual stages of the data path have the following latencies:
\begin{tabular}{|c|c|c|c|c|}
\hline IF & ID & EX & MEM & WB \\
\hline 250ps & 350ps & $150 p s$ & 300 ps & 200 ps \\
\hline
\end{tabular}
The registers that are used between the pipeline stages have a delay of 10 picoseconds each. Consider a program of 1000 instruction consists of approximately $25 \%$ loads, $10 \%$ stores, $13 \%$ branches, and $52 \%$ data-processing instructions. Assume that $40 \%$ of the loads are immediately followed by an instruction that uses the result, requiring a stall and that $50 \%$ of the branches are taken (mis-predicted), requiring a flush. Ignore other hazards. If branch outcomes are not known until EX stage, the total time to execute 1000 instructions on this pipeline is
$\qquad$ nanoseconds. (Rounded off to two decimal places)
