GATE CSE 2005 | Question: 80

Question

Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction "call Rn, sub” is a two word instruction. Assuming that $\text{PC}$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

$\text{Rn} \leftarrow \text{PC} + 1$;

$\text{PC} \leftarrow \text{M[PC]}$;

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

• A. $2$
• B. $3$
• C. $4$
• D. $5$

Comments

• Cycle 1: MAR ← PC; S ← PC

  • Reason: PC broadcasts; both MAR and S latch simultaneously.

• Cycle 2: MDR ← M[MAR]; Rn ← S + 1

  • Reason: Memory bus fills MDR while internal bus/ALU computes return address.

• Cycle 3: PC ← MDR

  • Reason: Load subroutine entry from MDR into PC.

Answer: 3 cycles.

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I was solving these question 2nd time with 6 month gap interval, still was not able to solve these question :)

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So bro not mug up things just clear your concept then you never forget the things....

Answer 1

• $\text{MAR} \leftarrow  \text{PC}\qquad \to1$ cycle
• $S \leftarrow \text{PC}$ (Since these two actions are independent they can be done in same cycle)
• $\text{MDR} \leftarrow \text{M[MAR]}\qquad \to 2^{nd}$ cycle (System BUS)
• $\text{Rn} \leftarrow S +1$ $(\text{ALU}$ Is free and the two actions are independent.) (Internal BUS)
• $\text{PC} \leftarrow \text{MDR}\qquad \to 3$rd cycle

Therefore $3$ cycles needed.

A rough sketch:

Correct Answer: B

Comments

But the question says that the Instruction is of 2 words, so 1st word is fetched during Fetch cycle, and the 2nd word of the instruction is fetched in the Execution cycle (Instruction Decode cycle) isn't it? Then 1 more cycle should be added to 3 cycles (4 cycles in total). Correct me if I am wrong.

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@Santanu02 While 1st word decoding is done 2nd word is fetched hence no additional cycle is required to fetch 2nd word. 

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@Riya Roy(Arayana) from where have u studied coa , especially data path and control units

Answer 2

_{Rn <= Pc+1}

_{Pc<= M[Pc]}

The sequence of instruction take place 

 

I Cycle : PC _out  , S_{in ,} MAR_in (MAR can be loaded with PCout

II Cycle: S _out  , ALUincrement  , R_{n in}

III Cycle: MDR_{out  ,}   PC_in  (MDRout can be performed once MARin has been performed)   therefore 3 cycle required

 

Comments

why we need to store PC value in MAR and Sin??and can we transfer PC content to Sin and MAR in same clock cycle?

Thanks

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Obviously we can store in same clock because once the content of PC is on bus both the registers MAR and S can activate their load input to take the data on the bus.

Answer 3

$T_0$ : $ MAR \leftarrow$ PC (via system bus)since MAR connected through System bus  

          $ S \leftarrow PC$ ( via internal nus)

$T_1$ : $ MDR \leftarrow M[MAR]$ {  Operation on system bus (address bus)}

$\\ R_N  \leftarrow S+1  \text{  Operation on internal bus }$  {can also be done with 3rd cycle}

$T_2$ : $PC \leftarrow MDR$ ( via system bus)

Note: MAR and MDR are Connected through System bus cannot done in One Cycle.

Comments

When doe we load 1 in to register for adding it to PC.As they have said ALU will do increment so ALU will take data from S and T register,when will we load 1 into T?

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@Prashant.
In Cycle To

"T0 : MAR←PC (via system bus)since MAR connected through System bus  
    S←PC ( via internal nus)"

You have done a mistake here as MAR and PC are not connected via system bus but by internal bus
We are actually performing this operation in clock T0 by putting the content of PC over internal bus and then enabling Load input of S and MAR in  same clock cycle i.e T0

Answer 4

Hi Guys,

Although many people have provided correct answer but It seems people want to see complete picture so just adding this answer.

So Answer is B part.

In above explanation $S$ is a temporary ALU register. Notice data to and from memory comes and goes via MDR that too via separate BUS.

If provided information is not correct then please notify.

Comments

@Chhotu ji

can u share the source, from where u given ans?

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can u share the source, from where u given ans?

@srestha ji,

This answer is not available anywhere. I derived it based on whatever is mentioned in question and standard text book.

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very nice explanation...but i have one doubt

the pc will increment to 2 in instruction fetch phase  or it will increment to 2 after instruction decode phase?

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Great solution considering the book Hamacher et al.

A correction by the way, the register Rn_in takes input from MAR_in

Answer 5

1)PCout ,MARin,Rin

2)MDRout ,PCin

2 cycles to read

so total 3  cycles

Comments

can you explain your answer somewhat..as i am not able to understand any of the answers.

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@Arjun Sir.

I am getting this. Question says, ”PC is incremented during the fetch cycle of the first word of the instruction”. So increment not needed during execution phase.

Please tell if this is correct or not.

T1: $PC_{OUT}, MAR_{IN}, Rn_{IN}, READ$

T2: $WMFC (i.e. MBR\leftarrow MEMORY)$

T3: $MBR_{OUT}, PC_{IN}$

 

Answer 6

In this question PC and GPR are carried out in the ALU.

So, PC and GPR performing write operation.

"call Rn, sub” - here subroutine call is performing , which is a memory read operation

And each memory read operation takes 2 clock cycle.

Then operation is performed in ALU.

$1)PC_{out},MAR_{in},Read,IncPC$

$2)WMFC$

$3)R_{2out},R_{3out},SelectA,SUB,R_{1in},END$

First two are FETCH cycle and 3rd one executing SUB instruction,i.e. EXECUTE cycle

Total 3 clock cycle

Comments

No. Here we have an indirect memory access M[PC]. So, PC content must be moved to MAR and then memory read needs to be done and read content moved to PC. See the answer by Pooja, other stuffs like also happen but these are the important ones to get answer here.

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In this question us memory bus separate from the data bus shown in the diagram?

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@Arjun Sir

Pc increment is done by Add instruction or is it other instruction which increments PC by 1.If it is a add instruction then we need to load data into  i.e 1 in T register also.And if it is INC instruction then it always increment by one.But word length can be more than one?I understand that ALU will not consume any extra cycle but the way we have loaded PC into S register,the same way why havent we loaded 1 into T register?

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@Arjun sir what does this line means PC is incremented during the fetch cycle of the first word of the instruction..? And why aren't we considering for second word of this instruction in our execution cycle..?I am bit confused please clear the question to me..thanks in advance sir