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GO CLASSES DPP | COA | Pipelining | UC San Diego

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A non-pipelined processor has the following stage latencies:
\begin{array}{|l|l|}
\hline Stage & Latency \\
\hline Fetch & 300 ps \\
\hline Decode & 400 ps \\
\hline Execute & 350 ps \\
\hline Memory & 550 ps \\
\hline Writeback & 100 ps \\
\hline
\end{array}

Assume no overhead between stages in the non-pipelined design.
Which of the following is correct regarding the non-pipelined processor?

  1. Cycle time $=550$ ps, Latency $=1700$ ps, Throughput $=1$ instruction every 550 ps
     
  2. Cycle time $=400 \mathrm{ps}$, Latency $=2000 \mathrm{ps}$, Throughput $=1$ instruction every 400 ps
     
  3. Cycle time $=1700 \mathrm{ps}$, Latency $=1700 \mathrm{ps}$, Throughput $=1$ instruction every 1700 ps
     
  4. Cycle time $=1700 \mathrm{ps}$, Latency $=550 \mathrm{ps}$, Throughput $=1$ instruction every 1700 ps

1 Answer

1 1 vote
In non-pipelined processor,  

Cycle time without storage buffers( no overhead) - 300 + 400 + 350 + 550 + 100 = 1700ps.

Every instruction has to go thorugh this much time in order to finish execution so latency = 1700ps

Throughput is for doing 1 instruction in 1700ps(if this is the unit time)

So option c should be correct.
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