Register

Gate 2016 digital
closed

• closed by
671 views
Voting & Accepting an answer helps improve the community
← PreviousNext →
← Previous in categoryNext in category →

Related questions

0 votes
0 votes
0 answers
1
aditi19 asked Nov 25, 2018
1,602 views
Digital Logic: GATE-ECE-2016
answer is 6 but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 ns where is extra 1 ns delay coming from?
answer is 6but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 nswhere is extra 1 ns delay coming from?
User Avatar
1 votes
1 votes
0 answers
2
s_tripathi asked Dec 26, 2017
1,242 views
Gate 2016 Set 1 Digital Logic 2's complement representation
Is 1's/2's complement valid only for negative numbers? If 2's complement of a number is 1111111111110101, then the number should be 0000000000001011. Then the decimal representation should be +11. But the answer is -11.
Is 1's/2's complement valid only for negative numbers? If 2's complement of a number is 1111111111110101, then the number should be 0000000000001011. Then the decimal rep...
User Avatar
8 votes
8 votes
1 answer
3
rahul sharma 5 asked Sep 10, 2017
7,618 views
Digital electronics ECE set-3 Gate 2016`
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero If the clock (Clk) frequency is 1GHz, then the counter behaves as a (A) mod-5 counter (B) mod-6 counter (C) mod-7 counter (D) mod-8 counter
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zeroIf the clock (Clk) frequency is 1GHz, then the...
User Avatar
0 votes
0 votes
0 answers
4
Ankita Shingala asked Oct 25, 2016
545 views
Digital logic
Following topics are there in GATE-CSE 2017 digital logic syllabus? 1: logic families 2: converters 3: semiconductor memories
Following topics are there in GATE-CSE 2017 digital logic syllabus?1: logic families2: converters3: semiconductor memories
User Avatar
Link Copied!