#co

Question

Within an instruction pipeline an RAW always creates one or more stalls ?? ture or false PLZ explain with example ??

Answer 1

first it is possible that RAW dependency never creates 1 or more stall.
ex is 

now there is a true(data) dependency between DADD and XOR instructions but they are not creating any stall.

Comments

Yes. But I guess the question assumes adjacent instructions. In that case is it true or false?

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@Arjun sir
threre are 3 types of instructions are possibles in our instruction set architecture these are
1. data transfer (load,store)
2. data manipulation (arithmetical and logical)
3. Transfer of control
now only 1 and 2 can results true data dependency(RAW)
suppose instruction J follows instruction I
case 1.    I: a load instruction
               J: a load or store instruction
now instruction I perform register write operation in write back stage. and instruction J perform register read in decode stage so without any extra assumption (like operand forwarding etc) it definitely creates RAW hazard.
case 2.   I; a data manipulation instruction
             J: a data manipulation instruction
now instruction I writes the data and it is done in write back stage(for reg.) or in memory access stage(in mamory operation) and instruction j read that is done in id stage so without any extra assumption (like operand forwarding etc) it definitely creates RAW hazard.
case 3***.     I; a data manipulation instruction
               J: a load or store  instruction
so as i can thnk there is always a RAW hazard. and also if it is not then it depends on pipeline hardware structure.

--------  plzz clarify me....