• edited by
31,408 views
86 86 votes

You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

7 Answers

63 63 votes

Ans- C.

 

• edited by
22 22 votes
B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.
8 8 votes

Explanation: We assume the D flip-flop to be negative edge triggered.

 
In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.
So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

 
Therefore, (C) is the correct answer.

5 5 votes

The inverter at f, and Q' will flip the waveform.
The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

 

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

Option C.

0 0 votes
Answer. C

Key lies in noting that there is a 90° phase lag -

1. between f and output of FF1 if it is positive edge triggered, since f changes for every negative edge.

2. between the two FFs as one is positive edge triggered and the other is negative edge triggered.

So,

A. FF1 output = ((f')') = f     and    FF2 output = f$\angle$ 90°

B. FF1 output  = f'$\angle$ 90°     and    FF2 output = f'$\angle$ 180° = f  (since f is a periodic digital signal with 50% duty cycle)

C. FF1 output  = f$\angle$ 90°      and   FF2 output = f$\angle$ 180°

D. FF1 output = f'                 and    FF2 output   = f'$\angle$ 90°

 

This explains the timing diagrams and @Arjun sir's answer.
Answer:
Position:
Show:

Related questions

42 42 votes
2 answers 2 answers
15.4k
15.4k views
Rucha Shelke asked Sep 22, 2014
15,390 views
Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$$x\bar{z}+xy+\bar{y}z$$x\bar{z}+xy+\overline{yz}$$xz+xy+\overline...
42 42 votes
8 answers 8 answers
25.4k
25.4k views
Rucha Shelke asked Sep 22, 2014
25,393 views
Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared).The following data: $100110000$ is suppl...
130 130 votes
11 answers 11 answers
33.7k
33.7k views
Rucha Shelke asked Sep 26, 2014
33,704 views
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray...
76 76 votes
6 answers 6 answers
30.0k
30.0k views
Rucha Shelke asked Sep 26, 2014
30,010 views
We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers i...