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+41 votes

You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

0

Anyone please give explanation. Should I draw timing diagrams and find the correct answer? @Arjun Sir,Please help

+2

Please do !! I am getting (A) as answer. According to me (c) results in phase shift by 360 degree. Since the function changes only at negative edges of clock, that change , in option(c), will be reflected at the output only in next negative clock pulse. So it takes entire clock cycle which means 360 degree phase shift. While in option (A) change in function at negative edge of clock is reflected in the next positive edge of clock which means change is reflected in just half clock pulse. So this shifts by 180 degree. But answer is given (C). I am not able to figure out what I am lacking in. Please clarify.

+8

**To understand what is duty cycle??**

https://en.wikipedia.org/wiki/Duty_cycle#/media/File:PWM_duty_cycle_with_label.gif

**What is phase delay of 180 degrees??**

The two waves are said to have a phase of 180 degrees if they are mirror image of each other

for e.g.

0

Duty Cycle - https://en.wikipedia.org/wiki/Duty_cycle (Observe Diagram)

50% means 1(Up) and 0(Down) period is equal.

Important Line ->

digital waveform f which changes only at the negative edge of the clock

changes only at the negative edge of the clock does not means it always changes.

+7

@gari ji ,

why did you remove [email protected] i think your explanation was precise.

OK adding again.

ping @VS, @shraddha_gami, @Puja Mishra, @srestha @Pronomita Dey 1 @iarnav and @Aaditya Pundir ji

+32 votes

0

How you created these waveforms?

I also tried but I am getting different waveforms.

Can you explain anyone of the waveforms only,rest I will do accordingly.

Thanks in advance :)

I also tried but I am getting different waveforms.

Can you explain anyone of the waveforms only,rest I will do accordingly.

Thanks in advance :)

+1

That's ok:)

See where I am getting confused is ::

1) Somewhere taking f and some where f complement (that can be managed)

2) Which FF is taken as which edge triggered ?( causing confusion)

3) What is the significance of negating the clock?

See where I am getting confused is ::

1) Somewhere taking f and some where f complement (that can be managed)

2) Which FF is taken as which edge triggered ?( causing confusion)

3) What is the significance of negating the clock?

+4

Negating a FF clock means that particular FF only become active during a negative clock edge and remain deactive during a positive colck edge.

0

But , final waveform and waveform of F are same .. Aren't they ? See from second clock cycle.

Also note Arjun sir's comment below :

B and D are inverting f and hence cannot be the answer.

+2

these are same from 2 clock cycle not from beginning. But we want exact same signal as F with 180 dealy.

OK.. apply F from 2nd clock cycle....Is there any difference..?? No... output is still same as above.

Inverting means same as F' not F.

OK.. apply F from 2nd clock cycle....Is there any difference..?? No... output is still same as above.

Inverting means same as F' not F.

0

Got it !! Thanx :)

One last thing how to calculate the phase difference?

One more thing is there a shortcut method for this or we have to draw all waveforms always?

One last thing how to calculate the phase difference?

One more thing is there a shortcut method for this or we have to draw all waveforms always?

0

Can you please check the waveform of option a.I think it should be 90 deg delay by** F'** and not F.Since for 2nd Flip flop input is **Q' **of first flip flop.

0

In option a

when the f' changes at negative clock signal then at the same time the D flip flop also changing? first flip flop should read the value of f' in the previous cycle instead of new as new change should be available at end of clock?

0

@Aaditya

I have a doubt that 50% duty cycle would mean that after getting output from first FF the wave is shifted by half the clock.... So when this is input to the second FF and output is generated... Will the output wave again shifted by half clock period..?? From your answer I mean that u shifted only once, the first time....

I have a doubt that 50% duty cycle would mean that after getting output from first FF the wave is shifted by half the clock.... So when this is input to the second FF and output is generated... Will the output wave again shifted by half clock period..?? From your answer I mean that u shifted only once, the first time....

0

I have a doubt regarding A waveform drawn.Please visit my last comment.I think it will get high at positive edge of 3rd clock. @VS can you please check

0

In option C)

Input of first FF is "F" so when first time we provide +ve edge then output of FF1 should be high till next +ve edge, and then low and continueu like this way. But you are taking Output of FF1 low. why??

Input of first FF is "F" so when first time we provide +ve edge then output of FF1 should be high till next +ve edge, and then low and continueu like this way. But you are taking Output of FF1 low. why??

0

how are you deciding from which clock cycle to start? I get it that C is producing same wave as F, but how and why is it starting from 2nd clock cycle?

+9 votes

B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.

0

Though I am also getting the answer to be (c), I have a doubt in your explanation. As per the question, f changes only at the negative edge of the clock. So, the time period of f is twice that of the clock. In option (a), during the negative clock, the first Flipflop inverts the complement of f (since the output is taken from ~Q (Q bar),).Hence the output phase is same as f. But the next flipflop delays it by half clock. So, f suffers a delay of 90 degrees in the second Flipflop. So, the output in option (a) does not have the same phase as f, but it is delayed by 90 degrees.

Plz correct me if I'm wrong.

Plz correct me if I'm wrong.

+1

I must have added I assumed negative edge triggered flip flop.

Now for A case, the output of first flip flop given to the next one is same as f due to double inversion. But is it of same phase? Also if a waveform is passed through a D flip flop using a clock which is in sync with the waveform, phase change happens?

Now for A case, the output of first flip flop given to the next one is same as f due to double inversion. But is it of same phase? Also if a waveform is passed through a D flip flop using a clock which is in sync with the waveform, phase change happens?

+1

As far as I know, double inversion doesn't change phase.

Also note that as per the notation used in the diagram, the first flip flop works at the negative level of the clock whereas the second flip flop works at the positive level of the clock.

I am attaching the timing diagram for option (a).

0

I also got the same timing diagram except for the final output where I took the FF as negative edge triggered.

" as per the notation used in the diagram, the first flip flop works at the negative level of the clock whereas the second flip flop works at the positive level of the clock"

Do you have a reference for this notion?

0

I read that in a book. A bubble is used along with a triangle to signify negative edge triggered. A normal line implies level triggered. You can see the notations here:

http://www.circuitstoday.com/triggering-of-flip-flops

Even if the flip flops are negative edge triggered, I think the final output must not change. If the first flip flop works on negative edge of the clock, the second flip flop will actually work on the positive edge of the original clock (or negative edge of the inverted clock); since the clock is inverted in the second flip flop.

really confusing though! :P

0

your final o/p is not correct. You are taking Q from first FF to be given as an i/p to second FF but actually it is Q' .

0

We know that,

1. Final DFF needs to trigger at the same clock edge as f, to be in a 180 phase. Hence second DFF gets neg, and first gets positive. (options A and D are out)

2. If you draw the timing diagram, value of f from previous clock needs to be passed down to final DFF. This can be done by i) initial DFF taking neg_f and and final DFF taking neg_D0 as input, or ii) initial DFF taking f and and final DFF taking D0 as input. This eliminates option B.

Hence C is the answer

0

@arjun sir

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

can't get these line

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

can't get these line

0

@Arjun sir, what does phase delay by 180 means?

Also ,when f changes on negative clock then how can d change on same clock?The updated value of F will be available to D on next clock cycle as in https://gateoverflow.in/264/gate2005-62 ?

+5 votes

**Explanation:** We assume the D flip-flop to be negative edge triggered.

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.

So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

Therefore, (C) is the correct answer.

+1 vote

The inverter at f, and Q' will flip the waveform.

The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

**Option C.**

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