210 ns wat I think will be the answer. The confrigation of this can be assummed like the assosiative cache as no other combinational circuit is given. we will identify the block number and then access the least 15 bit the data. So no of blocks in main memory = 2^20. so 20 bit is the size of TAG, one comparator for each row. and finally an or gate. comparartor will work in parllel. = 20+10 ns = 210ns