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9 votes
5 answers
22
ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time will the processor be slowed down due to DMA activity? $9.6$ms $4.8$ms $2.4$ms $1.2$ms
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time w...
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11 votes
3 answers
24
Cycle Stealing(DMA)
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
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11 votes
4 answers
25
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are $\textsf{INTR & INTA}$ $\textsf{RD & WR}$ $\textsf{S0 & S1}$ $\textsf{HOLD & HLDA}$
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR & INTA}$$\textsf{RD & WR}$$\textsf{S0 & S1}$$\textsf{HOLD & HLDA}$
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1 votes
2 answers
26
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 5 (Page No. 81)
On early computers, every byte of data read or written was handled by the CPU (i.e., there was no DMA). What implications does this have for multiprogramming?
On early computers, every byte of data read or written was handled by the CPU (i.e., there was no DMA). What implications does this have for multiprogramming?
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1 votes
2 answers
29
DMA & IO
DMA interface unit eliminates the need to use CPU registers to transfers data from (a) MAR to MBR (b) MBR to MAR (c) I/O units to memory (d) Memory to I/O units
DMA interface unit eliminates the need to use CPU registers to transfers data from(a) MAR to MBR (b) MBR to MAR(c) I/O units to memory (d) Mem...
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2 votes
3 answers
30
Ace Test Series: CO & Architecture - Instruction Execution
CPU can leave current instruction execution, without completing it for : Service of interrupt DMA Both Neither
CPU can leave current instruction execution, without completing it for :Service of interruptDMABothNeither
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4 votes
5 answers
34
ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
In DMA transfer scheme, the transfer scheme other than burst mode iscycle techniquestealing techniquecycle stealing techniquecycle bypass technique
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2 votes
4 answers
36
A hard disk with transfer rate of 20 kbps is constantly transferring data to memory using DMA cycle stealing mode
A hard disk with transfer rate of 20 kbps is constantly transferring data to memory using DMA cycle stealing mode. The size of data transfer is 32 bytes. The processor ru...
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1 votes
2 answers
40
MadeEasy Test Series
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