In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in
(D) is the correct answer!
~Source: Moris Mano
when s=r=0 it is latched. how it is ivalid !!
An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR latch.
invalid state mentioned here is indeterminate state,
what happens in indeterminate state is output keeps of changing between 0 and 1 infinitely
so we can not anything in latch or not decide what is stored in latch thats why the name indeterminate state.
If you want to prove to yourself how latch goes to invalid state, draw diagram, draw truth table, apply input and see it going infinitely
Q and Q' will come as 1 each which is an indeterminate state as the outputs are not complementary.
If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).
very good explanation of SR latch using NOR and NAND gate