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In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in

  1. $Q = 0, Q' = 1$
  2. $Q = 1, Q' = 0$
  3. $Q = 1, Q' = 1$
  4. Indeterminate states
asked in Digital Logic by Veteran (59.5k points) | 4.2k views
+11

(D) is the correct answer!

~Source: Moris Mano

9 Answers

+10 votes
Best answer
Answer should be C. The reasoning is as follows:

When both $R$ and $S$ are set as $0,$ we will get both $Q$ and $Q'$ as $1$ (these must be ideally mutually complementary).  This output will be permanent and is not dependent on any sequence of events but just the input values (so no race condition). But after this state if we enter both $R$ and S as $1,$ the output will be indeterminate depending on which NAND gate processes first (either $Q$ or $Q'$ will become $0$  but we can't determine which (race condition) and it will lead to an indeterminate state.

PS: $R = 0, S = 0$ in an SR latch made by cross coupling $2$ NAND gates will lead to a forbidden state. Forbidden state means, this state is invalid and must not be entered. This is different from an indeterminate state which means a state where we are not sure of the output. Again this is different from a toggling state where the output changes continuously.
answered by Junior (565 points)
edited by
+1
This should be the accepted answer.
0
only this ans should be true.
0
But , in latch , we have no control on the inputs since clock is not used in latch and we can't enter the inputs as our wish . The inputs will be some arbitrary external input through other parts of the circuit, which can be changing any time. so, it will not remain in (1,1) state, instead the state will become indeterminate.
0
The output will definetely fluctuate and becomes indeterminate.
+31 votes
If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).
answered by Boss (45.1k points)
+2
how race through?? Race through happens in JK flipflop where feedback inputs are present?? Here Q and Q bar gets stuck at same output which is invalid but how race through??
0
S R   Q Q
0 0 Latched
0 1 0 1
1 0 1 0
1 1 Metastable

when s=r=0 it is latched. how it is ivalid !!

0
I guess you are adding two more nand gate in front of the main latch ?
0
Yes. isn't it SR latch ? If so what it is called then ! Confused !!
+6

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR latch.

Ref::https://en.wikibooks.org/wiki/Digital_Circuits/Latches

0
Does anybody know the answer given in GATE keys? I think there's still confusion between option C and D.
+10 votes

SR latch with NAND

invalid state mentioned here is indeterminate state,

what happens in indeterminate state is output keeps of changing between 0 and 1 infinitely

so we can not anything in latch or not decide what is stored in latch thats why the name indeterminate state.

If you want to prove to yourself how latch goes to invalid state, draw diagram,  draw truth table, apply input and see it going infinitely

answered by Active (3.5k points)
+8 votes

Answer: D

Q and Q' will come as 1 each which is an indeterminate state as the outputs are not complementary.

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

answered by Boss (34k points)
+3
then why not option c too ??
0
isn't it a invalid state,

explain ??
0
+4 votes

very good explanation of SR latch using NOR and NAND gate

https://www.youtube.com/watch?v=kt8d3CYWGH4

answered by Loyal (7.6k points)
+3 votes

If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).

answered by Active (4.1k points)
+1 vote
D.)
Anybody who has read Morris Mano carefully can answer this in an instant!
answered by Active (1.5k points)
0 votes
answer - D
answered by Loyal (9k points)
–1 vote
IF ONE OF THE INPUT TO NAND GATE IS 0 THEN THE OUTPUT IS 1

SO Q=Q0=1
answered by Boss (10.9k points)
+1
so ans is C and D both ? as it is not possible Q1=Q0=1


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