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In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in

1. $Q = 0, Q' = 1$
2. $Q = 1, Q' = 0$
3. $Q = 1, Q' = 1$
4. Indeterminate states
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~Source: Moris Mano

If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).
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how race through?? Race through happens in JK flipflop where feedback inputs are present?? Here Q and Q bar gets stuck at same output which is invalid but how race through??
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S R Q Q 0 0 Latched 0 1 0 1 1 0 1 0 1 1 Metastable

when s=r=0 it is latched. how it is ivalid !!

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I guess you are adding two more nand gate in front of the main latch ?
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Yes. isn't it SR latch ? If so what it is called then ! Confused !!
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An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR latch.

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Does anybody know the answer given in GATE keys? I think there's still confusion between option C and D.

invalid state mentioned here is indeterminate state,

what happens in indeterminate state is output keeps of changing between 0 and 1 infinitely

so we can not anything in latch or not decide what is stored in latch thats why the name indeterminate state.

If you want to prove to yourself how latch goes to invalid state, draw diagram,  draw truth table, apply input and see it going infinitely

Q and Q' will come as 1 each which is an indeterminate state as the outputs are not complementary.

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

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isn't it a invalid state,

explain ??
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Answer should be C. The reasoning is as follows:

When we input both R and S as 0, then we will get both Q and Q' as 1. This output will be permanent and wont be fluctuating(so no race condition). But after that state if we enter both R and S as 1, the output will be indeterminate depending on which NAND gate processes first(race condition) and it will lead to an indeterminate state.
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This should be the accepted answer.
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only this ans should be true.
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But , in latch , we have no control on the inputs since clock is not used in latch and we can't enter the inputs as our wish . The inputs will be some arbitrary external input through other parts of the circuit, which can be changing any time. so, it will not remain in (1,1) state, instead the state will become indeterminate.
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The output will definetely fluctuate and becomes indeterminate.

If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).

very good explanation of SR latch using NOR and NAND gate

+1 vote
+1 vote
D.)
Anybody who has read Morris Mano carefully can answer this in an instant!
–1 vote
IF ONE OF THE INPUT TO NAND GATE IS 0 THEN THE OUTPUT IS 1

SO Q=Q0=1
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so ans is C and D both ? as it is not possible Q1=Q0=1