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GATE CSE 2004 | Question: 18, ISRO2007-31

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60 60 votes

In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in

  1. $Q = 0, Q' = 1$
  2. $Q = 1, Q' = 0$
  3. $Q = 1, Q' = 1$
  4. Indeterminate states

9 Answers

Best answer
88 88 votes
Answer should be C. The reasoning is as follows:

When both $R$ and $S$ are set as $0,$ we will get both $Q$ and $Q'$ as $1$ (these must be ideally mutually complementary).  This output will be permanent and is not dependent on any sequence of events but just the input values (so no race condition). But after this state if we enter both $R$ and S as $1,$ the output will be indeterminate depending on which NAND gate processes first (either $Q$ or $Q'$ will become $0$  but we can't determine which (race condition) and it will lead to an indeterminate state.

PS: $R = 0, S = 0$ in an SR latch made by cross coupling $2$ NAND gates will lead to a forbidden state. Forbidden state means, this state is invalid and must not be entered. This is different from an indeterminate state which means a state where we are not sure of the output. Again this is different from a toggling state where the output changes continuously.
• edited by
27 27 votes
If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).
9 9 votes

SR latch with NAND

invalid state mentioned here is indeterminate state,

what happens in indeterminate state is output keeps of changing between 0 and 1 infinitely

so we can not anything in latch or not decide what is stored in latch thats why the name indeterminate state.

If you want to prove to yourself how latch goes to invalid state, draw diagram,  draw truth table, apply input and see it going infinitely

9 9 votes

Detailed Video Solution: https://youtu.be/hRUnJKDVQ4M?t=8676&feature=shared

SR Latch Complete Lecture & ALL GATE CS-EC PYQs: https://youtu.be/hRUnJKDVQ4M 

In $SR$ Latch with NAND gates:

When $S=0$ and $R=0,$ both outputs of the latch are equal to $1$, i.e., $Q_S=1$ and $Q_R=1$. 

Thus, the two outputs are no longer complements of each other. This is undesirable as many of the circuits that we build with these latches rely on the assumption that the two outputs are always complements of each other. 

• An even bigger problem occurs when we transition from $S=R=0$ to $S=R=1$: Oscillations and Uncertain States.

• When $S=R=0,$ we have $Q_S=Q_R=1$. After the transition to $S=R=1$, however, we get $Q_S=Q_R=0$, which would immediately cause $Q_S=Q_R=1$, and so on. If the gate delays are Same, then this oscillation will continue forever. 

• In practice, the oscillation dies down and the output settles into either $Q_S=1, Q_R=0$ or $Q_S=0, Q_R=1$. The problem is that we can't predict which one of these two it will settle into.

Detailed Video Solution: https://youtu.be/hRUnJKDVQ4M?t=8676&feature=shared

Similar Questions: 

https://gateoverflow.in/1015/gate-cse-2004-question-18-isro2007-31

https://gateoverflow.in/3440/gate-it-2007-question-7

https://ec.gateoverflow.in/25/gate-ece-2017-set-1-question-15

https://ec.gateoverflow.in/2222/gate-ece-2007-question-44

https://ec.gateoverflow.in/1987/gate-ece-2009-question-38

https://ec.gateoverflow.in/3536/gate-ece-2023-question-24

SR Latch Complete Lecture & ALL GATE CS-EC PYQs: https://youtu.be/hRUnJKDVQ4M 

• edited by
8 8 votes

Answer: D

Q and Q' will come as 1 each which is an indeterminate state as the outputs are not complementary.

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

0 0 votes
IF ONE OF THE INPUT TO NAND GATE IS 0 THEN THE OUTPUT IS 1

SO Q=Q0=1
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