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A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

  1. 4 time units
  2. 6 time units
  3. 10 time units
  4. 12 time units

23 Answers

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Two 4 bit numbers are $A_{3}A_{2}A_{1}A{0}\ and\ B_{3}B_{2}B_{1}B{0}$ and their complements are also available.

Delay of each gate is one time unit.

 

Minimum time required for calculating $A\oplus B = A^{I}B+B^{I}A$ is

$A^{I}B$ and $B^{I}A$ are calculated parallel in one-time unit and their OR is calculated in one more time unit.

Total time = 2 units.

 

Propagation delay of Carry LookAhead adder can be analyzed through 3 levels.

Level 1: 

All Carry Propagators and Carry Generators $G_{i},P_{i}$ are calculated in two time units

$\\G_{i} = A_{i}\cdot B_{i}\\ P_{i} = A_{i}\oplus B_{i}$

 

Level 2:

$\\C_{0} = 0\\ C_{1} = C_{0}P_{0}+G_{0}\\ C_{2} = C_{0}P_{0}P_{1}+G_{0}P_{1}+G_{1}\\ C_{3} = C_{0}P_{0}P_{1}P_{2}+G_{0}P_{1}P_{2}+G_{1}P_{2}+G_{2}\\ C_{4} = C_{0}P_{0}P_{1}P_{2}P_{3}+G_{0}P_{1}P_{2}P_{3}+G_{1}P_{2}P_{3}+G_{2}P_{3}+G_{3}\\$

Every $C_{i}$ takes 2 units of time(1 AND followed by 1 OR) and they can be computed parallelly.

 

Level 3:

$\\S_{0} = C_{0}\oplus P_{0}\\ S_{1} = C_{1}\oplus P_{1}\\ S_{2} = C_{2}\oplus P_{2}\\ S_{3} = C_{3}\oplus P_{3}$

Let’s take a generalized one $S_{i} = C_{i}\oplus P_{i}$

                                              $S_{i} = C_{i}^{I}P_{i}+P_{i}^{I}C_{i}$

By the time we come to Level-3 we can compute the $P_{i}^{I}$ i.e while we are computing the things in Level-2

Now the things boil down to the question, can we compute $C_{i}^{I}$ in parallel with Level-2 operations.

Let’s take the $C_{3}$ and work on that

$C_{3}^{I} = (C_{0}^{I}+P_{0}^{I}+P_{1}^{I}+P_{2}^{I})(G_{0}^{I}+P_{1}^{I}+P_{2}^{I})(G_{1}^{I}+P_{2}^{I})G_{2}^{I}$

$\\G_{i}^{I} = (A_{i}B_{i})^{I}\\ P_{i}^{I} = A_{i}\odot B_{i} = A_{i}B_{i}+A_{i}^{I}B_{i}^{I}$.

Therefore $G_{i}^{I}\ and\ P_{i}^{I}$ can be computed parallely with Level-1 operations.

So we can compute $C_{i}^{I}$ with 1 OR followed by 1 AND, parallely with Level-2 operations.

Now $S_{i}$ can be computed in 2 time units having  $C_{i}^{I}\ ,C_{i},\ P_{i}^{I}\ ,C_{i}$ in hand after completing with Level-2 operations.

Therefore total time = Level-1 + Level-2 + Level-3

                                    = 2+2+2 = 6 units

 

Now let’s look at a specific case of each gate having FAN-IN = 2

Level-1 operations has no effect, they can be computed in 2 units.

Now here each $C_{i}$ doesn't have equal time units to compute.

$\\C_{3}\ time = log_{2}4(AND\ time)+log_{2}4(OR\ time) = 2+2 = 4\ units\\ C_{4}\ time = log_{2}5(AND\ time)+log_{2}5(OR\ time) = 3+3 = 6\ units$

Coming to Level-3

Same way $C_{i}^{I}\ and\ P_{i}^{I}$ are computed(as the approach mentioned above)

Therefore $S_{i}$ takes 2 time units.

And $S_{i}$ can be computed only when $C_{i}$ is available.

So $S_{3}$ computation takes (2+4+2) time units from begining and and also $C_{4}$ computation takes (2+6) time units from begining.

PS: We need not to wait for the $C_{4}$ to get complete for calculating $S_{3}$.

Then total time = 8 units

0 0 votes

🔧 Key Concepts in CLA

For each bit position ii, we define:

  • Generate (Gᵢ): Will this bit generate a carry?

Gi=Ai⋅Bi(AND gate → 1 unit)

  • Propagate (Pᵢ): Will this bit pass the carry forward?

Pi=Ai⊕Bi(XOR via AND-OR → 2 units)

  • Carry (Cᵢ): Computed using G and P values from previous bits. For example:

C1=G0+P0⋅C0

C2=G1+P1⋅G0+P1⋅P0⋅C0

These are built using 2-level AND-OR logic → 2 units

  • Sum (Sᵢ): Final output bit

Si=Pi⊕Ci(XOR → 2 units)

⏱️ Total Delay Breakdown

StageOperationDelay
1. Gᵢ and PᵢGᵢ: AND → 1 unitPᵢ: XOR → 2 unitsmax 2 units
2. Carry Cᵢ2-level AND-OR logic2 units
3. Sum SᵢXOR of Pᵢ and Cᵢ2 units

➡️ Total delay = 2 (G/P) + 2 (Carry) + 2 (Sum) = 6 time units

0 0 votes

The correct answer is B. 6 time units.

Here is the step-by-step analysis of the propagation delay:

1. Signal Generation ($P_i$ and $G_i$)

First, we need to generate the Propagate ($P_i$) and Generate ($G_i$) signals from the inputs $A_i$ and $B_i$.

  • Generate ($G_i$): $G_i = A_i \cdot B_i$. This requires 1 AND gate.

    • Delay = 1 unit.

  • Propagate ($P_i$): For the Carry Network logic, the condition $P_i = A_i + B_i$ (OR gate) is sufficient.

    • Delay = 1 unit.

  • Status: At $t=1$, valid $P_i$ and $G_i$ signals are available.

2. Carry Network ($C_i$)

The problem states the carry network is implemented using two-level AND-OR logic.

  • The carry equations (e.g., $C_{i+1} = G_i + P_i C_i$) are realized as Sum-of-Products.

  • Level 1 (AND gates): Takes inputs $P, G, C_{in}$. Ready at $t = 1 (\text{input}) + 1 (\text{gate}) = 2$.

  • Level 2 (OR gates): Takes outputs from ANDs. Ready at $t = 2 + 1 = 3$.

  • Status: At $t=3$, all Carry signals ($C_1, C_2, C_3, C_4$) are available.

3. Sum Generation ($S_i$)

The sum is given by $S_i = A_i \oplus B_i \oplus C_i$. This is a 3-input XOR operation. Since we only have AND/OR/NOT gates, we implement this using the Sum-of-Products expression:

 

$$S_i = \bar{A}\bar{B}C + \bar{A}B\bar{C} + A\bar{B}\bar{C} + ABC$$

 

This structure requires two levels of logic (AND-OR), but it requires the inputs $A, B, C$ and their complements $\bar{A}, \bar{B}, \bar{C}$.

  • Inverting $C_i$: We have $C_i$ at $t=3$. To get $\bar{C_i}$, we need a NOT gate.

    • $\bar{C_i}$ ready at $t = 3 + 1 = 4$.

  • AND Layer: The AND gates for the Sum logic need $C_i$ (ready at 3) and $\bar{C_i}$ (ready at 4). The bottleneck is $\bar{C_i}$.

    • AND outputs ready at $t = 4 + 1 = 5$.

  • OR Layer: The final OR gate sums the AND outputs.

    • Sum ($S_i$) ready at $t = 5 + 1 = \mathbf{6}$.

Overall Propagation Delay: 6 time units.


 

Visual Timeline

 

  • t = 0: Inputs $A, B$ arrive.

  • t = 1: $P, G$ generated.

  • t = 3: Carries $C_i$ generated (via 2-level logic).

  • t = 4: Inverted Carries $\bar{C_i}$ generated.

  • t = 5: Sum product terms generated.

  • t = 6: Final Sum $S_i$ generated.

0 0 votes

as per the diagram, propagation take 2 stage delay and generation takes 1 stage delay but overlaps with propagation delay so total 2 stage delay before carry generation, carry genertion takes 2 stage delay and lastly sum generation takes 2 stage delay, So overall delay is 6 stage delay.

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