The Gateway to Computer Science Excellence
+2 votes

Clock Q0 Q1 Q2 State
  0 0 0 0
1 1 0 0 1
2 0 1 0 2
3 1 1 0 3
4 0 0 1 4
5 1 0 1 5

At clock t5 or lets say after 5 clock pulses Q0 and Q2 becomes 1 and through NAND gate they will become 0 and since preset is active low will set the contents to 000

Doubt - When will this happen? In clock t5 only? or in the next clock t6. What is the significance of connecting clock with NAND gate?

If the output is cleared in t5 only then MOD will be 5 if it happens in t6 then MOD will be 6.

Ideally we clear the flip flops in the same clock and hence 101 will not be a state. So the counter should be MOD-5 I guess. But does connecting clock to the gate play any significance role?

 Doubt is similar to the one of the gate questions asked prviously :

in Digital Logic by Active (3.2k points)
retagged by | 842 views

@Praveen Sir  Could you please help with question? It is similar to the one you solved here -

clk will be 0 only because flip flop is triggered by negative clock.

i am also confused that whether it will be mod 5 or mod 6
it should be 5 as it is asyn.  counter and next state won't last untill the next clock pulse applied. it will be resetted in same clock itself.

made easy explanation

1 Answer

0 votes
How can you say pr is preset or clear. pr is active low but saying it is preset gives mod value 8. I have doubt regarding whether it is preset or clear? You'll thankful if you help me?
by (345 points)

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,737 questions
57,258 answers
104,735 users