Question

Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Design the cache structure with all pertinent information and show how it interprets the processor’s addresses.

Answer 1

No. of entries in cache = 4K

Line size = 2 *16 = 32 bits = 1 word, for byte addressing (which is default) we need 2 offset bits to address 4 bytes.

So, number of cache lines = 4K

Number of lines in a set = 4 (4 way set associative)

So, number of sets = 4K / 4 = 1024.

So, we need lg 1024 = 10 set/index bits and 2 offset bits. Remaining 12 (24-10-2) bits must be tag bits.

Comments

but 1 word is of 32 bit..and you are accsessing on 16 bit by that address

---

"so if we have to search 1 word of main memory in cache ...by ur defination it would take two addresses. "

Well, can you make this questions clear?

In word addressing the smallest unit CPU can address is a word. So, suppose 32 bits is a word, there won't be any offset bit and when CPU gives an address, it gets 32 bit data for it. (This obviously increases the amount of memory CPU can address and in turn requires more tag bits). The problem here is, to do byte operations CPU requires extra instructions. 

In byte addressing the smallest unit is a byte. Here also, from memory data is accesses as a page and with cache, the page is stored there (not byte). From the cache/memory using offset bits, a byte can be given to the CPU. 

---

Why offset bits are 2 for 4 bytes if it is byte addressable?