GATE CSE 2007 | Question: 36

Question

The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):
$$\small {\begin{array}{|c|c|c|c|l|}\hline
\textbf{Clear}&    \textbf{Clock}&  \textbf{Load}&\bf{ Count}& \textbf{Function}\\\hline
1&\text{X}&\text{X}&\text{X}&\text{Clear to 0} \\
0&\text{X}&0&0&\text{No Change}\\    
0&\uparrow&1&\text{X}& \text{Load Input} \\    
0&\uparrow&0&1& \text{Count Next} \\ \hline  
 \end{array}}$$
The counter is connected as follows:

     

Assume that the counter and gate delays are negligible. If the counter starts at $0,$ then it cycles through the following sequence:

• A. $0, 3, 4$
• B. $0, 3, 4, 5$
• C. $0, 1, 2, 3, 4$
• D. $0, 1, 2, 3, 4, 5$

Comments

No no, the counter starts at 0, if the load was =1 then the input would have loaded and the sequence would be 0,3,4

But, as the load =0 so the i/p is never loaded into the counter so it counts from 0,1,2,3,4 and when 5 comes the clear makes it 0000.

So, the sequence is 0,1,2,3,4 i.e., (C)

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No, the initial value was never loaded as load =1, so 3 is never considered

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count is 1 which means that it increments the value by 1

load is 0 means the input wont be loaded onto the output.

if the clear is 0 then all the inputs will be 0.

the iteration starts from 0 and then proceeds 1 ,2,3,4 as the clear is 1 depending upon A3 and A1 .

now, when it reaches 4 then increments as count is 1 and hence reached 5 but now clear became 0, so all the inputs will be instantly made 0, 5 will be present for very less time (almost negligible).

hence, the cycle sequence goes like 0,1,2,3,4 and then back to 0 and it continues, 5 is not reachable.

Answer 1

Whenever  $A4 A3 A2 A1 =0 1 0 1,$ clear line will be enabled as $A3$ and $A1$ are set.

Given table says that whenever clear control signal is set, it clears to $0 0 0 0,$ before the current clock cycle completes.

So, $5$ is cleared to $0$ in the same clock cycle and counter sequence is $0, 1 , 2, 3, 4$

Hence, option C .

Comments

@xylene As it is mentioned , input will get loaded only when load = 1 . So even though 0011 is given as input it won't get loaded as load = 0.

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can anyone explain how to read the table ?

I could not understand how to draw conclusions from the table .

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Ruchi Vora

X means "any value - either 0 or 1 ". Up arrow means "a clock pulse"

Here we need only the 1st and last row of the table.

1st row says that, For any value of clock, load, count and if clear value =1 then "clear to 0". ie we set output to zero.

And last row says that, if there is a clock pulse and if clear =0, load =0 and count =1 then  "count next". ie we increment the output by 1.

Counter starts from 0 and it counts 1 2 3 4 5 as the configuration fixed (last row of the table). When count reaches 5, configuration changes to 1st row. Since there is no counter and gate delay, we won't be able to see 5 in output. So it is like a counter that counts the sequence  0 1 2 3 4

 

Answer 2

(C) is the correct answer!

$Remark:$
1. If $clear = 1$, counter will be reset to 0000 $\underline{\text{without any delay, and counter doesn't count 5}}$.
2. If $load=1$, counter will be loaded with the input 0011, but note that $\underline{\text{counter counts 5 in this case}}$ unlike clear input.
3. Counter counts from $0$ to $4$.
4. Clear and Load are direct inputs, it means they can be applied to the counter without using any pulse.

 

When the output reaches the count of 1001, both A0 and A3 become 1, making the output of the AND gate equal to 1. This condition activates the Load input; therefore, on the next clock edge the register does not count, but is loaded from its four inputs. Since all four inputs are connected to logic 0, an all‐0’s value is loaded into the register following the count of 1001. Thus, the circuit goes through the count from 0000 through 1001 and back to 0000, as is required in a BCD counter.

In Fig (b), the NAND gate detects the count of 1010, but as soon as this count occurs the register is cleared. The count 1010 has no chance of staying on for any appreciable time, because the register goes immediately to 0.

1. If $clear=1$, then clear the counter.
2. If $clear=0, load = 0, count = 1,$ counter counts.
3. $load = 1,$ loads the input to the counter.

If $load = 1$, then counter will be loaded with $i/p = 0011$

to the given counter, $count = 1, load = 0, clock = \uparrow$

 

$\underline{\text{Note:}}$ If o/p of $\textsf{AND}$ gate is led to $load$, then counter will be loaded with $0011$.

Comments

@Manu Thakur Sir,

in the case of   BCD counter using clear input , clear is also getting enabled for 0001,0011.

how is this correct?

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Yeah it is always 0, except 1001 , 1101 , 1111

Answer 3

Using the following 2 arguments we can conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

2)

 The output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

 

So, 5 is cleared to 0 in the same clock cycle.

so counter sequence is 0, 1 , 2, 3, 4

Hence option C .

Comments

What is the significance of 0011 at input?

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No significance

read above comments by Bikram sir , jst below question

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@VS can you explain the statement "we need to add delay to clear logic equal to 1 time period of clock pulse".

Answer 4

ans is D:

given input is 0011     

A1 & A3 is 0, so clear=0. now as per last row of table count will be next count. initially counter was 0 now it will become 1.

now 1 will be the input 0001. here A1&A3 is 0, so clear is 0. and again counter will be increased to 2.

now 2 will be the input 0010. here A1&A3 is 0, so claer is 0. and again counter will be increased to 3.

now 3 will be the input 0011. here also A1&A3 is 0. so counter will become 4.

now 4 will be the input 0100. here also A1&A3 is 0. so counter will become 5.

now 5 will be input 0101. here A1&A3 is 1. so clear will become 1. As per first row of table counter will reset to 0 again.

hence ans is D.

Comments

Why given i/p "0011" doesnt affect here. Why we havent considered it as 0, 4,5 as an answer.. (Ignore options for some time)

Why?

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"If the counter starts at 0, then it cycles through the following sequence:"is given in the question, i think in the diagram they just want to illustrate some state

Answer 5

Caption

 

Answer 6

This is 4bit synchronous counter which works according to the table as described. But how the counter is working is kept hidden(Black boxed). This is a positive edge triggered counter, means it will work only on +ve edge of the clock only (Assuming it because of given ↑ in the clock) and the initial input=0 and count=1, load=0 initially given in the figure. Now check the function table and try to figure out the action of this counter.
The initial input to the counter is 0(A4=0,A3=0,A2=0,A1=0)(given in question if the counter starts with 0), count =1, load=0, clear=A1.A3=0

Now check the function on these inputs.

Function= count next, which will become 1,

similarly, now input to the counter=1(A4=0,A3=0,A2=0,A1=1), count=1, load=0, clear=0

Function= count next which will become 2

similarly then it will count 3 then 4 but

But when counter will increament from 4 to 5(A4=0,A3=1,A2=0,A1=1), the clear=A1.A3=1 so CLEAR=1 and input will be reset immediately to 0 because of negligible delay of the gate and for that enrite clock cycle the counter value will be 0(for a fraction of time it is 5). So the counter counts from 0 to 4.

Comments

hey, i have one doubt does binary counter counts like 0,1,2,3,4,5…