1 votes 1 votes How to calculate the total gate delay for 16 bit adder using 4, 4 bit CLA? Question source:https://en.wikipedia.org/wiki/Carry-lookahead_adder reena_kandari asked Jul 18, 2017 reena_kandari 1.1k views answer comment Share Follow See 1 comment See all 1 1 comment reply joshi_nitish commented Jul 18, 2017 reply Follow Share it depends on max value of fan-in... 1 votes 1 votes Please log in or register to add a comment.
0 votes 0 votes The delay depends on the Fan in of AND gate used, i.e If n Bit numbers are added using CLA where k is Fan in of AND gate used, then T(n) = logk n Please correct me if i am wrong. AnilGoudar answered Jul 18, 2017 AnilGoudar comment Share Follow See all 3 Comments See all 3 3 Comments reply joshi_nitish commented Jul 19, 2017 reply Follow Share you are correct if there is single CLA but there are several other factors also to be considered in this qsn, here adder is made up of 4, 4bit CLA... each CLA can work in logkn time but it has to wait for preceeding CLA to provide carry bit and hence total time taken will be Nlogkn, where N are nos of CLA rippled together... it can be seen that although each CLA work in parrellel way but they have to wait for preceeding CLA(to provide carry bit which can be used as C0).. therefore it is hybrid mixture of parrellel and ripple adder.. 0 votes 0 votes AnilGoudar commented Jul 19, 2017 reply Follow Share @joshi_nitish, Yes, We have to consider the ripple factor N which indicates, How many times a CARRY has to ripple through the adder, since we have 4,4 bit CLA. Since each CLA gets carry from previous CLA, here can we say N=3 ? as there is no need of ripple carry for first CLA. Please correct me if iam wrong. Is my understanding correct? 0 votes 0 votes joshi_nitish commented Jul 19, 2017 reply Follow Share yes, you are correct... 0 votes 0 votes Please log in or register to add a comment.