Gate q-43_44

Question

Consider a cache memory hit ratios for read and write operations are 80% and 90% respectively. If there is a miss then 2 word block is to be through from main memory to cache. Consider 30% updations and the cache access time is 20ns/word and memory access time 100 ns/word.

Q43 calculate the efficiency of the cache using write through scheme?

A. 13.8 million words/ sec

B 12.8 million words/sec

C 14.8 million words/sec

D 11.8 million words/sec

Q 44 find efficiency of cache using write back scheme?( in million words per sec)

A.15.5    b. 16.5    c. 14.5     d. 13.5

Answer 1

1. Write through

$T_{read} =  20 + 0.2 \times 2 \times  100= 60 ns$

$T_{write} = 100 ns$ (Write through always goes to memory, so hit rate does not matter for time and only 1 word is written to)

$T_{avg} = 0.7 \times 60 + 0.3 \times 100 = 72 ns$

So, $\text{throughput} = \frac{\text{Amount of data transferred}}{\text{time taken}} \\= \frac{1}{72 \times 10^{-9} }\\ = 13.8 \text{million words per second}$.

Efficiency is a ratio - should be a mistake in question. 

2. Write back. To solve this we need amount of dirty bits or percentage of dirty page replacement. This is missing in question. 

See 35154 for reference. 

Comments

Why Twrite = 100ns it only happens when Hit ratio for write is 1.

In this question it seems he is using Hirearical write operation where he is first bringing the block in cache and then updating both cache and mem. Simultaneously.

 

Tavg write= .9*100 + .10(2*100+100) = 120ns.

 

If it is mentioned in the question that simultaneously wirte is done then Tavg write should be 100ns.

 

Please suggest if I am doing wrong

 

Thanks in Advance

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@Arjun sir how did you understand that what is the orientation of memory devices? How to understand whether it is hierarchical or simultaneous access for both read and write from the question? Can you please explain this?

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@gshivam63

here Tread = Hr*TC + (1-Hr)*(2*Tm+TC)

because when a read miss occurs first cache is searched, and as it is a miss 2 words are read from the main memory. So the main mempry is accessed two times for the reading of two words but the access to cache is only once prior to that and not two times.

Using this formula,

 Tread=0.8*20+0.2*(2*100+20)=16+44=60ns

which is the same as the value obtained by using the simplified formula as done by Arjun sir.

Answer 2

I happen to differ from Arjun Sir.
Please let me know my faults, if any.

Taking for write through
T(avg read)= Hit ratio (read)* access time of CM+ Miss ratio (read)*(Read allocate time+ access time of CM)

And,
T(avg write)= Hit ratio (write)*write through time + miss ratio (write)*(write allocate+write through time)

Because write/read allocate as given in the question is to get 2 word block to be transferred from MM to CM. Taking read/write allocate as 2*100ns

And write through time is max (Tm, Tc)= 100ns

So
T read= 0.8*20+0.2(100*2+20)
            =60ns
T write= 0.9*100+0.1(100*2+100)
             =120ns
Tavg= 0.7*60+0.3*120
         =78ns
Tavg is time for 1 word access
Therefore, in one second

1000/78 million words will be accessed on average.

This evaluates to 12.8 million words/second.
Hence, option b.

Comments

I don't think we need to consider miss during write, in write through cache. In write through hit ratio always considered as 1.

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No, the question asks you to consider it.

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I don't see any need of doing this, here hit ratio for write operation is given only for write back scheme, also we need % of dirty bits for calculating write time in write back.  Usually more data than required word is tranferred to the cache in case of read operation , to make use of locality of reference. 

So unless it is mentioned, for transferring more data in write operarion we can consider only one word access. As it was in this question - https://gateoverflow.in/10668/64-word-cache-and-main-memory-is-divided-into-16-words-block

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You have taken hierarchal access for read and simultaneous for write.But as per questions both are hierarchal.

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How did you understand that what is the orientation of memory devices? How to understand whether it is hierarchical or simultaneous access for both read and write from the question? Can anyone please explain me this?

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When hit write ratio for a memory organization = 1 then the memory is considered to be simultaneous memory organization and when the question specifically states the hit write ratio = some x value then the memory organization is taken as hierarchical organization so in this case 12.8 million words/sec is the right answer.