Throughput in Pipelining means number of instructions that can be executed per second. Answer to your question is maybe or maybe not.
Lets take an example of a pipelined processor with 4 stages having below delays: 3ns, 5ns, 10ns and 5ns.
Frequency of clock= 1/Maximum delay = 1/10ns = 0.1 GHz
Thus, in ideal conditions 1 instruction comes out in 10ns.
Throughput = 10^8 instructions/second
The above formula is the key here.
Case 1: Stage 3 is broken down into two stages with delay 5ns each. Frequency now? 0.2 GHz.
Throughput=2*(10^8) instructions/second
So throughput has been increased successfully.
Case 2: We break down stage 2 into 3ns and 2ns. What is the frequency now? Still 0.1 GHz. So throughput remains same.
This happened because we didn't break the stage with largest delay.
I hope you got my point now.
