Cache memory

Question

Consider a scenario, where there is 2 level cache in a memory hierarchy.

1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instructions, then there will be 140 memory accesses. Here my question is how memory accesses can be more than number of instructions?

2)Secondly, suppose for this application, the miss rate of L1 cache is 0.1. What is meaning of miss rate here? Is miss rate on instructions or miss rate on memory accesses? If it is miss rate on memory accesses, why not we calculate it miss rate on number of instructions?

3)Here in the (level 2 cache) L2 cache experiences, on average, 6 misses per 1000 instructions. Now,  here 1000 instruction is for level 2 cache, but why we will take it as total number of instruction present in memory? I mean memory can work on 2000 instruction too, but only 1000 is for L2 cache . right?

4) What miss rate is for L1,L2 and total in this memory hierarchy? Is it not number of misses in total number of instructions?

Answer 1

To begin with, you forgot to include a reference to the correct question, so here it is to help other readers

https://gateoverflow.in/118305/gate2017-1-25

Here is my best attempt to explain

1) A single instruction is divided into multiple stages (pipelined or non pipelined). These are

• Instruction Fetch
• Instruction Decode
• Operand Fetch
• Execute
• Write Back the result

Our of above, memory access takes places in below

• Instruction Fetch
• Instruction Decode
• Operand Fetch
• Execute
• Write Back the result

So, for a single instruction memory is access thrice. Depending upon the architecture and design, this may vary. 

2 ) A miss is a miss and is it always means that "something" could not be found on cache and thus a memory has to be accessed. This "something" can be an instruction and a data.

3) Nowhere the question says that L2 takes all instructions present in memory. So the assumption that L2 takes all instructions in memory is not correct. And if we take total instructions as 1000, then the instructions coming to L2 would be calculated appropriately (There is not a way that I know to do that though.)

4) From the answer to above question

• L1 miss rate = 0.1
• L2 miss rate = 0.05
• What do you mean by "Total miss rate". Is it Instructions for which data could not be retrieved from cache ? Then we can find that using below

There were total 1400 memory references, out of which 140 were missed by L1 and out of these 140, 7 were missed by L2. So out of 1400 memory references, 7 were missed by both caches and so main memory reference had to be made. Which comes out to be 0.5 

Comments

yes , mostly understood