The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 are performing multiplications, where Excution state for addition take 1 clock cycle, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline has 5 stages IF, ID, EX, MA and WB and their is no data and control hazard. The number of clock cycles required for execution of sequence of instructions are ________.
Ans. 454