Consider a pipeline processor with 5 stages, Instruction Fetch (IF). Instruction Decode and Operand Fetch (ID), Operation performed (OP). Data memory access (MA) and Write back (WB). The IF, ID, MA and WB stages takes 1 clock cycle each for any instruction. The OP stage takes 1 clock cycle for ADD and SUB instructions and takes 3 clock cycles for MUL instruction. The minimum number of clock cycles are needed to complete following sequence of instruction if operand forwarding is used ________.