CAO ME

Question

 

Consider a pipeline processor with 5 stages, Instruction Fetch (IF). Instruction Decode and Operand Fetch (ID), Operation performed (OP). Data memory access (MA) and Write back (WB). The IF, ID, MA and WB stages takes 1 clock cycle each for any instruction. The OP stage takes 1 clock cycle for ADD and SUB instructions and takes 3 clock cycles for MUL instruction. The minimum number of clock cycles are needed to complete following sequence of instruction if operand forwarding is used ________.

 

Answer 1

15 clock cycles

Comments

after which stage in 1st instruction are you performing operand forwarding? looks like after memory acess(ma).. but the answer given is 11.

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yes..if OP to OP forwarding is done..then 11 clock cycles.

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but it is not given in the question, what do we need to assume if it is not given..

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its usually given in the question. If not, then we have to take best case i guess.
Ref-
https://gateoverflow.in/102565/operand-forwarding-in-pipeline