GATE-2000

Question

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that
(A) T1 <= T2 (B) T1 >= T2

(C) T1 < T2 (D) T1 is T2 plus the time taken for one instruction fetch cycle

The answer given in all sources is B.
The answer should be C acccording to me.As it is told we are comparing the time taken by a  single instruction And because of the buffers in the different stages of the pipelined system would’nt  it take more time than the time a single instruction would take to execute in a non-pipelined system  as it has only one unit.(I AM COMPARING ONLY THE TIME TAKEN BY A SINGLE INSTRUCTION).

Answer 1

It has been given that the CPU's are identical , with only one difference , one has a pipelined architecture , i.e while some unit e.g the decoding is happening , instruction fetch and PC increment unit can be carried out in the same clock cycle(of course with the use of interstage buffer) , and the other CPU has a non-pipelined architecture , i.e no sharing of clock cycles takes place.

We can safely take into assumption that no interstage buffer is being used in the non-pipelined architecture.

Let's say both the CPU's have 5 stage data path , namely $IF , ID , IE, M , WB$.

Let's say each stage takes $x \ clock \ cycles$.

In case of pipelined processor , let the interstage buffer delay = $y \ clock \ cycles$.

Total clock cycles for execution of an instruction in pipelined architecture(T1) = $5x+4y$ clock cycles.

Total clock cycles for execution of an instruction in non-pipelined architecture(T2) = $5x$.

In this scenario , T1>T2.

Now if non-pipelined architecture too had interstage buffers , then total time would've been = $5x+4y$.

In this scenario , T1= T2.

Thus $T1>=T2$ shall be correct.

Pipelining speeds up in long run , for only one instruction it is as good as non-pipelined version.