Caching closed

Question

Given the following information:
• TLB hit rate 95%, TLB access time is 1 cycle.
• cache hit rate 90 %, cache access time is 1 cycle.
• When TLB and cache both get miss; page fault rate is 1%
• The TLB access and acache access are sequential.
• Access to main memory required 75 cycles
• Access to hard drive requires 50,000 cycles.
Compute the average memory access latencies when the cache is physically addresses (in cycles).

Comments

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Why u don't use cage hit?

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Avg Mem access:  TLB Hit{ (TLB acess time) + (Cache Hit* Cache access time) + (Cache Miss* (Cache + Memory access time))} + TLB Miss* { (TLB access time) + (Page table access) + (Cache Hit * Cache Access) + (Cache Miss * ( Page Hit * ( Cache Access + Memory Access)) + (Page Fault * (Cache Access + Memory Access + Page fault Service Time))}

Avg Memory Access =  .95(1 + .9(1) + .1(1+75)) + 0.05( 1+ 75 + 0.9(1) + 0.1( 0.99(1+75) + 0.01 ( 1+ 75 + 50,000))

= 15.75 cycles