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Caching [closed]

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Given the following information:
• TLB hit rate 95%, TLB access time is 1 cycle.
• cache hit rate 90 %, cache access time is 1 cycle.
• When TLB and cache both get miss; page fault rate is 1%
• The TLB access and acache access are sequential.
• Access to main memory required 75 cycles
• Access to hard drive requires 50,000 cycles.
Compute the average memory access latencies when the cache is physically addresses (in cycles).
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in CO and Architecture by (417 points)
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