1 1 vote CO & Architecture co-and-architecture pipelining data-dependency + – Himanshu1 4.5k views answer comment Share Follow Print See all 2 Comments 2 2 Comments reply resuscitate commented Dec 24, 2015 reply Follow flag is it 11?? 0 0 replyShare Himanshu1 commented Dec 24, 2015 reply Follow flag Answer given is 14. 0 0 replyShare Please log in or register to add a comment.
0 0 votes Inst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I1 IF ID DF EX WB I2 IF ID DF EX WB I3 IF ID DF STALL EX WB I4 IF ID STALL DF STALL EX WB I5 IF STALL ID STALL DF STALL EX WB I6 STALL IF STALL ID STALL DF STALL EX WB All I3 I4 I5 I6 dependent. Umang Raman answered Dec 24, 2015 Umang Raman comment Share Follow See all 10 Comments 10 10 Comments reply Himanshu1 commented Dec 24, 2015 reply Follow flag I3- DF can't happen before I2-WB So, I3-DF should happen at 6 Change subsequent Instrustions accordingly. 1 1 replyShare Umang Raman commented Dec 24, 2015 reply Follow flag What is DF here? 0 0 replyShare Himanshu1 commented Dec 24, 2015 reply Follow flag Data Fetch , I think. 2 2 replyShare resuscitate commented Dec 24, 2015 reply Follow flag yeah,then ans will be 18.though i completely agree with u @amar 1 1 replyShare Umang Raman commented Dec 25, 2015 reply Follow flag yah if it is DF is after WB then cycle will be increased. 0 0 replyShare Himanshu1 commented Dec 25, 2015 reply Follow flag I3- DF & I2-WB can happen together , so Answer should be 14. So, Umang U hv to modify the Table.. Or Can I modify ur table ? 0 0 replyShare Umang Raman commented Dec 25, 2015 reply Follow flag how they can overlap untill I2 dont write back the date how I3 will fetch it ? 0 0 replyShare Himanshu1 commented Dec 25, 2015 reply Follow flag Becz, u must have read that writes take place in first half cycle & read (DF) takes place in second half of a clock cycle. 0 0 replyShare Umang Raman commented Dec 25, 2015 reply Follow flag but in question it is mentioned no special hardware technique and whatever you mentioned is only available in RISC pipeline . and according to me data fetching can be done before wb coz it just accessing the register file i think . execution will be done at ex stage so at that time new data required so it will be kept after wb. 0 0 replyShare Himanshu1 commented Dec 25, 2015 reply Follow flag I am not sure whether that is special Hardware(In that case 18 should be the answer) or by default , and Indeed we are talking about RISC pipeline only , just that no special technique for Hazard resolution. But for sure we can't DF before WB of previous instruction (in case of RAW Hazard) becz it will read old values , if operand forwarding is not employed.. 0 0 replyShare Please log in or register to add a comment.
0 0 votes 5 for first instruction 1 for second instruction and 1+2 for third instruction(depends on 2 therefore 2 stalls) 1+2 for fourth(depends on third ) 1+2 for fifth(depends on 4th) 1+2 for sixth(depends on 5th) total = 18 cycle sachin486 answered Aug 8, 2020 sachin486 comment Share Follow 0 reply Please log in or register to add a comment.
