Consider a byte addressable memory with $16$ bit addresses and a $2$- way set associative $\mathrm{L} 1$ cache of size $8 \mathrm{ kB}$ (kilobyte). Each cache line is $4$ words long. A process sequentially accesses the following memory addresses:
$\textsf{0x1000, 0x1004, 0x1010, 0x11C0, 0x2000, 0x3000, 0x1006, 0x2001}$
Assuming the $\mathrm{L} 1$ cache is initially empty and the LRU (least recently used) page replacement policy is used, indicate whether the cache access will result in a hit or a miss for each of the above addresses.