GATE CSE 2008 | Question: 36

Question

Which of the following are NOT true in a pipelined processor?

1. Bypassing can handle all RAW hazards
2. Register renaming can eliminate all register carried WAR hazards
3. Control hazard penalties can be eliminated by dynamic branch prediction

• A. I and II only
• B. I and III only
• C. II and III only 
• D. I, II and III

Comments

bypassing cant handle all RAW hazards

Register renaming can eliminate WAW and WAR dependancy in single execution pipeline

dynamic branch prediction can only decrease the possibility of control hazards but can't completely eliminate it.

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Bypassing is the same as forwarding.

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@Vortex thanks 

Answer 1

(B) I and III

I - False    Bypassing can't handle all RAW hazard, consider when any instruction depends on the result of LOAD instruction, now LOAD updates register value at Memory Access Stage (MA), so data will not be available directly on Execute stage.

II - True, register renaming can eliminate all WAR Hazard.

III- False, It cannot completely eliminate, though it can reduce Control Hazard Penalties

Comments

Thats correct. But dynamic branch prediction can eliminate almost 99% of control hazards :)

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Didn't knew Arjun sir that optimizations have improved so much :)

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My team lead is the world champion on branch prediction competition :) He owns the best branch predictor.

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@Arjun Sir:Plz give a scenario where bypassing can't handle a RAW hazard...

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when there are three instructions and 3rd instruction reads the values written by first instruction.

also when there are 2 instructions with RAW dependency and first instruction is a load/store instruction.

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But bypassing can eliminate RAW as operand forwarding can be done from memory stage too by adding another input at mux before input to ALU

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@Arjun sir any refrence for branch prediction
because I have read somewhere that delayed branch prediction can also be used to remove hazards

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sir i think answer should be 1 st only as control hazards can be elimineted by dynamic branch pridiction but as option is not given thats why I and 3 rd right ?

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Register renaming can handle all WAR hazards?Can you share some reference for this point?It didnt find this point in my book.And on internet they are saying it is not possible to completely remove WAR with register renaming

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not refrence but i have studied as if their is WAR hazards like R1<-- r2 + r3 & r2 <--- r3 + r5 we can rename second R2 to resolve this conflict so depandency get resloved

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If more no of physical register (i.e. sufficient to use in multiple instructions) is not available, can register renaming solve WAR and WAW always?

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@ rahul sharma 5 Register renaming can handle all WAR hazards?  is it possible to completely remove WAR with register renaming ..?

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yeah it as possible to remove completely WAR and  WAW hazards the only RAW hazards cant be removed completely

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Refer this https://gateoverflow.in/167016/co-test-series-true-false-statements

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@Arjun sir, I think answer should be A) because

statement III) is saying  Control hazard penalties can be eliminated by dynamic branch prediction it is not saying that It will always eliminate Control hazards., as you also said that 99% time it works so it can, but not always.(1%)---->so TRUE

statement II) suppose we have limited number of registers but our programme is so large that required registers for renaming are much larger. than register renaming will fail here.I don't know this scenario is practically  possible or not but theoretically It might be fail.

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Register renaming can not only eliminate WAR hazard but also WAW hazard ...

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always? @vicky

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@ reena_kandari yes 

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@reena_kandari,

we have limited number of registers but our program is so large that required registers for renaming are much larger. than register renaming will fail here.

First of all good point. But we do not execute entire program in one shot. For example if we have 5 stage in pipe line then only 5 different instruction can execute in parallel that to in different stage of pipe line. Now Based on processor instruction set it could be calculated in worst case how much register could be used.  So if  processor has that many number of register then OK otherwise Renaming it self could not be done and Hazard may come. 

@Vicky rix ji @reena_kandari and @VS ji what is your opinion ?

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@chhotu, you might be correct but  this is topic of CO, so we can't say what is exactly used in Architecture.There may be many other things going while CPU is executing a set of instructions.CPU may be executing many other programs concurrently..or we can say lots of instruction concurrently and if we use same finite set of registers Then I think it will be a overhead of using those same registers for renaming(due to lots of context switching and load/store instruction back to memory)

read this,

From a computer architecture point of view, an additional problem for write-after-read hazards is dealing with load and store operations to main memory. Register renaming won't help with this problem

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for 1st option    , after load operation in MA cycle can't we pass the the value to execution cycle by operand forwarding through buffer  ??   what is the problem here in removing RAW HAZARD . plz explain

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yes I) could be true

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please don't copy paste from other sites :P

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Useful link

https://compas.cs.stonybrook.edu/~nhonarmand/courses/sp16/cse502/slides/08-superscalar_ooo.pdf

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@Prateeksha Keshari  operand forwarding not possible for the case mentioned by you but in this question https://gateoverflow.in/1391/gate2005-68 operand forwarding is possible from MA to EX. Please explain the scenario here ... Thank you

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Branch prediction, frequency of missprediction near to 0 in nASA7.

Still its not 100%

Thats the benchmark in 2019

Reference: Advanced Computer Architecture Hennessy and Patterson.

 

Also good READ:  https://www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture/Lectures/pdfs/Ch04-AdvCompArch-BranchPrediction-PaulKelly-V03.pdf

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@reena_kandari you are right. Renaming can’t eliminate the hazards caused by load instructions due to limited number of registers availability. 

Ref.: https://cs.stackexchange.com/questions/30108/does-register-renaming-remove-all-kinds-of-war-hazard

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i have a doubt.
Register renaming can elimate all WAR hazards? True 
Register renaming can eliminate all WAW hazards?

@GO Classes

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@param_modi yes it can bcz both have common sol 

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WAR and WAW both will be eliminated because these hazards occur due to reordering of instructions when we try to eliminate true dependencies...so to address this, we use temporary registers to store intermediate values which allow us to use those values without data loss, thereby eliminating both WAR and WAW hazards.

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Register renaming cannot eliminate all WAR WAW hazards. It can eliminate all register carried  WAR and WAW hazards but not of memory locations. And that's why the question is specifically asking about register carried dependencies.

Reference NPTEL Page 7

 

Answer 2

Bypassing (also called forwarding) cannot handle all RAW (Read After Write) hazards.

Let’s explain clearly:

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What is a RAW hazard?

A Read After Write (RAW) hazard occurs when an instruction needs to read a value from a register before a previous instruction has written its result to that register.

Example:

1. ADD R1, R2, R3   ; R1 = R2 + R3
2. SUB R4, R1, R5   ; R4 = R1 - R5   ← Needs result of previous instruction

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What is bypassing/forwarding?

Bypassing means taking the output of an instruction directly from a pipeline stage (like EX or MEM), before it is written back to the register file, and sending it to the next instruction that needs it.

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Bypassing can handle:

• Most RAW hazards where the value is needed in EX stage and is available from the previous instruction’s EX/MEM/WB stages.

For example:

1. ADD R1, R2, R3   ; EX stage produces R1
2. SUB R4, R1, R5   ; Needs R1 in EX → Forward from EX/MEM

This can be handled by forwarding.

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 Bypassing cannot handle:

• Cases where the consumer instruction is too close, and the producer hasn’t computed the result yet.

Example with load-use hazard:

1. LW  R1, 0(R2)    ; R1 gets data from memory (available in MEM stage)
2. ADD R3, R1, R4   ; Needs R1 in EX stage

Here, R1 is not ready in time for instruction 2’s EX stage, because the load instruction gets data only at the end of MEM.

Even with bypassing, the second instruction must be stalled for one cycle.

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Conclusion:

• Bypassing can handle most RAW hazards.

• But not all — especially load-use hazards need stalls.

Comments

VERY WELL EXPLAINED

 

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Nice Explanation :) 

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nice explanation

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In statement3 it is written that "can be eliminated" not surely but yes it can then this statement stands true?

Answer 3

The correct answer is: II and III only

Explanation:

I. Bypassing can handle all RAW hazards:

• True. Bypassing (also known as data forwarding) is a technique in pipelined processors to mitigate data hazards. It allows the result of an instruction in a later stage of the pipeline to be directly forwarded to an earlier stage that needs that result. This helps in handling Read-After-Write (RAW) hazards and improving pipeline efficiency.

II. Register renaming can eliminate all register-carried WAR hazards:

• False. Register renaming helps in eliminating Write-After-Read (WAR) hazards, not Register-Carried Write-After-Read (WAR) hazards. Register renaming is a technique that assigns multiple physical registers to a single architectural register to allow independent execution of instructions, preventing write-after-read hazards. However, it does not eliminate all register-carried WAR hazards.

III. Control hazard penalties can be eliminated by dynamic branch prediction:

• False. While dynamic branch prediction can significantly reduce the impact of control hazards, it cannot eliminate all control hazards. Dynamic branch prediction techniques aim to predict the outcome of branches and speculatively execute instructions based on those predictions. However, mispredictions can still occur, leading to control hazard penalties.

Therefore, the correct answer is "II and III only."

 

 

 

 

Answer 4

Ans