GATE CSE 2025 | Set 1 | Question: 17

Question

A partial data path of a processor is given in the figure, where $\text{RA, RB,}$ and $\text{RZ}$ are $32$-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

 

• A. The data path can implement arithmetic operations involving two registers.
• B. The data path can implement arithmetic operations involving one register and one immediate value.
• C. The data path can implement arithmetic operations involving two immediate values.
• D. The data path can only implement arithmetic operations involving one register and one immediate value.

Comments

A, B and C are correct,, https://correctbrain.com/buy/

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Nice analysis

 

Answer 1

(A), (B) & (C)

we can choose any input from 1 MUX. and we have different select lines for MUX A & MUX B. hence we can have both registers as input, 1 register 1 immediate value as input, or both immediate value as input.
hence, there is no compulsion of 1 input as immediate value and other from register hence option D is false

Answer 2

The data path of a processor includes three 32-bit registers: RA, RB, and RZ. Two multiplexers control the inputs to the ALU:

• Mux_A selects between RA and a 32-bit immediate value  
• Mux_B selects between RB and a 32-bit immediate value

The output of the ALU is written to register RZ. The ALU supports standard arithmetic operations such as addition and subtraction under appropriate control signals.The structure of the data path allows independent selection of both operands fed into the ALU:

• Operand A $∈$ { RA, $\texttt{imm₁}$ }  
• Operand B $∈$ { RB, $\texttt{imm₂}$ }

Since each multiplexer operates independently, all four combinations of operand sources are physically supported by the hardware:

1. RA and RB  
2. RA and immediate  
3. Immediate and RB  
4. Immediate and immediate

For each case, the ALU computes the result and stores it in RZ. There is no structural limitation in the data path that prevents any of these combinations from being realized.

$$
\begin{array}{|l|c|l|}
\hline
\textbf{Operand Combination} & \textbf{Supported?} & \textbf{Reason} \\
\hline
\text{RA and RB (register--register)} & \text{Yes} & \text{Set Mux A to RA, Mux B to RB} \\
\hline
\text{RA and immediate} & \text{Yes} & \text{Set Mux A to RA, Mux B to immediate} \\
\hline
\text{Immediate and RB} & \text{Yes} & \text{Set Mux A to immediate, Mux B to RB} \\
\hline
\text{Immediate and immediate} & \text{Yes} & \text{Set Mux A to imm}_1, \text{ Mux B to imm}_2 \\
\hline
\end{array}
$$

Therefore, arithmetic operations involving:

• two registers  
• one register and one immediate  
• two immediates  

are all implementable within the constraints of the given data path.

Statement D: The data path can only implement arithmetic operations involving one register and one immediate value  

• This claims exclusivity, but other combinations are possible → False

 

$$
\color{lime} \boxed{\text{A, B, and C are correct}}
$$

Comments

@parity doesn't we need to consider storing of arthematic operaiton ?

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No , the operation to be performed is not stored its decoded via opcode which is then sent to ALU by use of control signals.
https://www.robots.ox.ac.uk/~dwm/Courses/2CO_2014/2CO-N3.pdf can refer to these notes for better understanding 

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@parity thank you

Answer 3

Option A): The data path can implement arithmetic operations involving two registers (RA and RB).

Option B): The data path can implement arithmetic operations involving one register and one immediate value.

Option C): The data path can implement arithmetic operations involving two immediate values.

Option D): Incorrect, as the data path is not limited to only one register and one immediate value.

So, options A), B), and C) are correct.