y not ans 33.6 *10^3 microsecond??????????????

y The first carry and sum will be available after 4.8 us & how???????????

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+49 votes

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.

0

y not ans 33.6 *10^3 microsecond??????????????

y The first carry and sum will be available after 4.8 us & how???????????

0

here mention xor is twice of and/or so and/or is 1.2ms so xor is 2.4 ms & 1 hald adder is 1xor+1and so= 3.6

& a full adder is implemented wt 2 half adder +1 or gate = 2*3.6+1.2= 8.4

4full adder =4*8.4= 33.6

& a full adder is implemented wt 2 half adder +1 or gate = 2*3.6+1.2= 8.4

4full adder =4*8.4= 33.6

+6

okay :) If everything is done one after the other or in a serial way. But, operations can be done in parallel- you can see the figure given below. As long as input to a gate is not dependent on the output from another gate, those two can be operated in parallel.

+1

Should not this be like since in the question we are given that a full adder is here implemented as 2 Half adders and an OR gate..

And we know that if we follow this constraint of circuitry then we use cascading half adders and then an OR gate..So delay should be added for each of the half adders and one OR gate for every full adder implementation.

So delay of a full adder should be : 2.4 * 2[For 2 half adders] + 1.2 [for OR gate]

= 6 ms

So delay of 4 bit ripple carry adder = 4 * 6 ms

= 24 ms

@Arjun Sir , please check this approach..

And we know that if we follow this constraint of circuitry then we use cascading half adders and then an OR gate..So delay should be added for each of the half adders and one OR gate for every full adder implementation.

So delay of a full adder should be : 2.4 * 2[For 2 half adders] + 1.2 [for OR gate]

= 6 ms

So delay of 4 bit ripple carry adder = 4 * 6 ms

= 24 ms

@Arjun Sir , please check this approach..

0

what will be the difference if i use ripple carry adder over Carry look ahead adder here?? what will be the chenge in aswer??

0

@ S Ram,

The question itself says,

"A 4-bit-ripple-carry binary adder is implemented by using four full adders"

I think it should be clear now.

The question itself says,

"A 4-bit-ripple-carry binary adder is implemented by using four full adders"

I think it should be clear now.

+1

Delay of carry look ahead adder:

https://gateoverflow.in/35865/total-propagation-delay-in-carry-look-ahead-adderin-a-4-b

+89 votes

$S1$ should wait for $C1$ to be ready. Delay for generating $C$ is $1$ EXOR $+ 1$ AND $+ 1$ OR $= 2.4 + 1.2 + 1.2 = 4.8$ $μs$

Delay for sum is XOR + XOR $= 2.4 + 2.4 = 4.8 μs$

But for the second adder, there the first EXOR can be done even before waiting for the previous output. So, we can get the sum in Another $2.4 μs$ and carry in another $2.4 μs$. In this way, $4$-$bit$ sum can be obtained after

$4.8 μs + 3 * 2.4 μs = 12 μs.$

But the question says we use ripple-carry adder. So, each adder must wait for the full output from the previous adder. This would make the total delay $= 4 * 4.8 = 19.2 μs$ and this is the key given by GATE, so obviously they meant this.

Reference: http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/adder.html

+1

For this question, time we get carry from last full adder is $4*4.8=19.2\mu s$

You are asking what is total propagation delay for a 4-bit ripple carry binary adder whose sum is produced in $4.8 \mu s$ and carry in $5.2 \mu s?$

Carry to the last full adder would come after $3*5.2 \mu s$ and then output carry would be produced in another $5.2 \mu s$ and hence total propagation delay=$4*5.2 \mu s$

You are asking what is total propagation delay for a 4-bit ripple carry binary adder whose sum is produced in $4.8 \mu s$ and carry in $5.2 \mu s?$

Carry to the last full adder would come after $3*5.2 \mu s$ and then output carry would be produced in another $5.2 \mu s$ and hence total propagation delay=$4*5.2 \mu s$

0

@Arjun sir,

if they ask for how much time is going to take for generating sum then writing direct

4*4.8doesn't make good sense it should be written like[3*4.8(carry)+4.8(sum by last FA)]. which leads to definately 19.2.

0

@Arjun Sir,

The answer considered for evaluation is $12$ but as explained above it's $19.2$ please update.

+1

0

@Devendra Thakur

This would make the total delay =4∗4.8=19.2μs and this is the key given by GATE,

so obviously they meant this.....

This would make the total delay =4∗4.8=19.2μs and this is the key given by GATE,

so obviously they meant this.....

0

@Arjun Sir

Please correct this answer.

The best way to analyse this answer is by drawing a detailed representation of the "gates."

Earlier the answer given by gate authority is 19.2 but later on after evaluation they changed it to 12.

+1

Just check out my answer below. You will understand it very well as I have drawn it very neat and clean.

In the mean time I will provide you the updated key.

This is the wrong answer and I wonder how it can be the best answer considering the excellent quality of all other questions on the gateoverflow.

I am just waiting for the Arjun Sir to take a note of this question or to have a conversation.

Hopefully this will get correct soon.

0

Just check out my answer below. You will understand it very well as I have drawn it very neat and clean.

In the mean time I will provide you the updated key.

This is the wrong answer and I wonder how it can be the best answer considering the excellent quality of all other questions on the gateoverflow.

I am just waiting for the Arjun Sir to take a note of this question or to have a conversation.

Hopefully this will be corrected soon.

0

@Arjun sir which method should we go for if it is asked in exam? Isn't the formula for ripple carry adder total propagation time

(n-1)xTc + Ts ? So according to that we get 19.2 micro seconds. But according to the diagram it is clear that 12 micro seconds should be the answer. I am really confused.

+25 votes

Ans is 12 ns

It took me a while but here's how it is :

The first carry and sum will be available after 4.8 ns. This should be straight forward.

However, for the subsequent stages, you need to keep in mind that the output of half adders is already there at 2.4 ns. So in a sense, it is already computed. The remaining half adder for each full adder is just waiting for the previous carry, which when available from the previous stage can be processed in 2.4 ns. So each next stage will take only 2.4 ns each.

The catch here is that half of the output in each next stage is already computed, only half needs to be processed.

It took me a while but here's how it is :

The first carry and sum will be available after 4.8 ns. This should be straight forward.

However, for the subsequent stages, you need to keep in mind that the output of half adders is already there at 2.4 ns. So in a sense, it is already computed. The remaining half adder for each full adder is just waiting for the previous carry, which when available from the previous stage can be processed in 2.4 ns. So each next stage will take only 2.4 ns each.

The catch here is that half of the output in each next stage is already computed, only half needs to be processed.

0

https://electronics.stackexchange.com/questions/153650/delay-in-4-bit-ripple-carry-adder

I see what you did there :p

Oh and btw, your very first solution is the correct one, It's according to Gate's official answer key...

0

"The remaining half adder for each full adder is just waiting for the previous carry, which when available from the previous stage can be processed in 2.4 ns. So each next stage will take only 2.4 ns each."

yes..but the previous carry will be available after another 2.4ns and then second XOR will happen which will take another 2.4ns. In total it will take 4.8ns

+3 votes

This should be the right procedure to get the right answer for this question.

Simply putting the formula here won't work.

Therefore, the answer comes out to be 12 microseconds.

+1 vote

**b) 19.2**

**C(i+1)=(A XOR B).C(i)+A.B**

Hence Totla delay of one carry bit is

1 XOR gate + 2 AND gate + 1 OR gate

2.4 +1.2+1.2 =4.8 microsec.

1) total delay from c1 to c4 will be 4.8 x 4 =19.2 microsecond;

2) total delay from c1 to c3 + sum of A4 and B4 will be 4.8 x 3+ (2.4+2.4) =19.2 microsecond

hence for** MAX DELAY** =**MAX**( 19.2,192 )

**MAX DELAY** is 19.2 microsecond.

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