GATE CSE 2015 Set 1 | Question: 37

Question

A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ flip-flop, while the $Q$ output of the $JK$ flip-flop is connected to the input of the $D$ flip-flop. Initially, the output of the $D$ flip-flop is set to logic one and the output of the $JK$ flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the $Q$ output of the $JK$ flip-flop when the flip-flops are connected to a free-running common clock? Assume that $J = K = 1$ is the toggle mode and $J = K = 0$ is the state holding mode of the $JK$ flip-flops. Both the flip-flops have non-zero propagation delays.

• A. $0110110\ldots$
• B. $0100100\ldots$
• C. $011101110\ldots$
• D. $011001100\ldots$

Answer 1

Caption

Answer is A......

Answer 2

$Q_{1}^+ =\mathbf{D}=Q_2, \ Q_{2}^+ = \mathbf{JQ_2'+K'Q_2}= Q_1Q_2'+Q_1'Q_2=Q_1\oplus Q_2$
 

$$\begin{array}{|c|c|c|c|} \hline \bf{Q_1} & \bf {Q_2}& \bf {Q_1^+=Q_2} &  \bf{Q_2^+=Q_1\oplus Q_2 }\\\hline1&0&0&1\\ 0&1&1&1\\1&1&1&0\\ 0&0&0&0\\\hline\end{array}$$

$Q_1$ $Q_2$ $:10\rightarrow01\rightarrow11\rightarrow10$

Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop

$011011011....$

Correct Answer (A)

Answer 3

The circuit given can be designed as:

State table can now be generated as:

Q0	Q1	Q0N	Q1N
0	0	0	0
0	1	1	1
1	0	0	1
1	1	1	0

Now, transition diagram is:

Since, the output is tapped at Q1, So, output will be (including the initial state '0' at D- FF): 0110110....

Correct Answer: (A).

 

Answer 4

1. Initial State:

   • $D$ flip-flop: $Q = 1$
   • $JK$ flip-flop: $Q = 0$
   •  

2. First Clock Pulse:

   • $D$ flip-flop: Inputs $J$ and $K$ of $JK$ flip-flop are both $1$ (from $Q$ of $D$ flip-flop).
   • $JK$ flip-flop: Toggles to $Q = 1$.
   • $D$ flip-flop: Updates its input to $1$ (from $Q$ of $JK$ flip-flop), but its output $Q$ remains $1$ due to non-zero propagation delay.
   •  

3. Second Clock Pulse:

   • $D$ flip-flop: Inputs $J$ and $K$ of $JK$ flip-flop are both $1$ (from $Q$ of $D$ flip-flop, which is still $1$).
   • $JK$ flip-flop: Toggles back to $Q = 0$.
   • $D$ flip-flop: Updates its input to $0$ (from $Q$ of $JK$ flip-flop), but its output $Q$ remains $1$ due to the delay.
   •  

4. Third Clock Pulse:

   • $D$ flip-flop: Inputs $J$ and $K$ of $JK$ flip-flop are both $0$ (from $Q$ of $D$ flip-flop, which is still $1$ due to the delay).
   • $JK$ flip-flop: Remains in state-holding mode, $Q = 0$.
   • $D$ flip-flop: Now updates its output $Q$ to $0$ (from $Q$ of $JK$ flip-flop in the previous clock cycle).
   •  

5. Cycle Repeats:

   • The same pattern continues, generating the sequence $0110110...$