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+30 votes

A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ flip-flop, while the $Q$ output of the $JK$ flip-flop is connected to the input of the $D$ flip-flop. Initially, the output of the $D$ flip-flop is set to logic one and the output of the $JK$ flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the $Q$ output of the $JK$ flip-flop when the flip-flops are connected to a free-running common clock? Assume that $J = K = 1$ is the toggle mode and $J = K = 0$ is the state holding mode of the $JK$ flip-flops. Both the flip-flops have non-zero propagation delays.

- $0110110\ldots$
- $0100100\ldots$
- $011101110\ldots$
- $011001100\ldots$

+31 votes

Best answer

$${\begin{array}{|c|c|c|l|}\hline

\bf{Q_{prev}}& \textbf{D}& \textbf{Q(JK)}&\bf{Explanation} \\\hline

\text{-}&1&0&\text{Now, the D output is 1, meaning J and K = 1; for next cycle} \\\hline 0&0&1& \text{J = K = 1(D output from prev state), so output toggles from 0 to 1} \\ \hline 1&1&1&\text{J = K = 0, so output remains 1} \\ \hline 1&1&0& \text{J = K = 0, so output remains 1} \\ \hline 0&0&1& \text{J = K = 1, so output toggles from 0 to 1}\\ \hline 1&1&1& \text{J = K = 0, so output remains 1} \\ \hline

\end{array}}$$

D flipflop output will be same as its input and JK flipflop output toggles when 1 is given to both J and K inputs.

i.e., $Q = D_{prev}({Q_{prev}}') + ({D_{prev}}')Q_{prev}$

Correct Answer: $A$

\bf{Q_{prev}}& \textbf{D}& \textbf{Q(JK)}&\bf{Explanation} \\\hline

\text{-}&1&0&\text{Now, the D output is 1, meaning J and K = 1; for next cycle} \\\hline 0&0&1& \text{J = K = 1(D output from prev state), so output toggles from 0 to 1} \\ \hline 1&1&1&\text{J = K = 0, so output remains 1} \\ \hline 1&1&0& \text{J = K = 0, so output remains 1} \\ \hline 0&0&1& \text{J = K = 1, so output toggles from 0 to 1}\\ \hline 1&1&1& \text{J = K = 0, so output remains 1} \\ \hline

\end{array}}$$

D flipflop output will be same as its input and JK flipflop output toggles when 1 is given to both J and K inputs.

i.e., $Q = D_{prev}({Q_{prev}}') + ({D_{prev}}')Q_{prev}$

Correct Answer: $A$

+15 votes

D |
Q_{D} |
Q_{JK} |
J |
K |
Q^{+}_{JK} |
---|---|---|---|---|---|

0 | 1 | 0 | 1 | 1 | 1 |

1 | 0 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 1 | 1 |

Answer = **A** = 01101101....

+4 votes

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