66 66 votes A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ flip-flop, while the $Q$ output of the $JK$ flip-flop is connected to the input of the $D$ flip-flop. Initially, the output of the $D$ flip-flop is set to logic one and the output of the $JK$ flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the $Q$ output of the $JK$ flip-flop when the flip-flops are connected to a free-running common clock? Assume that $J = K = 1$ is the toggle mode and $J = K = 0$ is the state holding mode of the $JK$ flip-flops. Both the flip-flops have non-zero propagation delays. $0110110\ldots$ $0100100\ldots$ $011101110\ldots$ $011001100\ldots$ Digital Logic gatecse-2015-set1 digital-logic flip-flop normal + – Misbah Ghaya 21.0k views answer comment Share Follow Print See all 4 Comments 4 4 Comments reply usher commented Dec 9, 2024 reply Follow flag the output of jk is connected to input of d while output of q is connected to jk jk here behaves like toggle, when the input if 1 it outputs ~q when 0 q. d has input = output. the sequence matches with option a. 0 0 replyShare You_Should_achieve 🫵 commented Nov 19, 2025 reply Follow flag Does cleared mean value is 0 initially at j and k ? 1 1 replyShare js__ commented Jan 12 reply Follow flag o/p of JK FF is initially 0 ----------> suppose Q1o/p of D FF is initially 1 ----------> suppose Q0@siddardha_Annapuredd 1 1 replyShare GO Classes Support commented Aug 23 reply Follow flag Watch the Detailed Video Solution by clicking the button below..!Watch Detailed Video Solution 2 2 replyShare Please log in or register to add a comment.
Best answer 57 57 votes $${\begin{array}{|c|c|c|l|}\hline \bf{Q_{prev}}& \textbf{D}& \textbf{Q(JK)}&\bf{Explanation} \\\hline \text{-}&1&0&\text{Now, the D output is 1, meaning J and K = 1; for next cycle} \\\hline 0&0&1& \text{J = K = 1(D output from prev state), so output toggles from 0 to 1} \\ \hline 1&1&1&\text{J = K = 0, so output remains 1} \\ \hline 1&1&0& \text{J = K = 0, so output remains 1} \\ \hline 0&0&1& \text{J = K = 1, so output toggles from 0 to 1}\\ \hline 1&1&1& \text{J = K = 0, so output remains 1} \\ \hline \end{array}}$$ $\text{D}$ flipflop output will be same as its input and $\text{JK}$ flipflop output toggles when $1$ is given to both $\text{J}$ and $\text{K}$ inputs. i.e., $Q = D_{\text{prev}}({Q_{\text{prev}}}') + ({D_{\text{prev}}}')Q_{\text{prev}}$ Correct Answer: $A$ Arjun answered Feb 15, 2015 • edited Jun 19, 2021 by Lakshman Bhaiya Arjun comment Share Follow See all 10 Comments 10 10 Comments reply Show 7 previous comments ananthsaibhargavtata commented Jan 20, 2025 reply Follow flag Clearly stated that assume with no propagation delay. If propagation delay exists answer varies . Variations u can solve and comment out . 0 0 replyShare 13Dev commented Nov 13, 2025 reply Follow flag @ananthsaibhargavtata @Rishabh1006 "Both the flip-flops have non-zero propagation delays." 0 0 replyShare Deepak Poonia commented Aug 20 reply Follow flag NOTE:For this type of question, the propagation delay doesn't matter, whether it is zero or non-zero, because both the flip-flops are edge-triggered & we have synchronous circuit here.Since both the flip-flops are edge-triggered, & we know that the active clock edge (here positive edge in this question) occurs once in each clock cycle, the Next state is determined from the inputs present at the clock edge (to be precise, at each active clock edge, flip-flops use the input values present just before that edge due to setup time issue, explained HERE)Since we have synchronous circuit here, Both FFs effectively respond to their inputs simultaneously. 1 1 replyShare Please log in or register to add a comment.
23 23 votes Correct option: A Rishav Kumar Singh answered Sep 18, 2018 Rishav Kumar Singh comment Share Follow See all 4 Comments 4 4 Comments reply Rishav Kumar Singh commented Oct 2, 2018 reply Follow flag this question is similar to https://gateoverflow.in/118315/gate2017-1-33 0 0 replyShare techbrk3 commented Oct 20, 2018 reply Follow flag Why Q0 is taken as MSB and Q1 is taken as LSB in FF diagram. ?, Any specific reason. What if Q0 is taken as LSB and Q1 as MSB, we get same answer (sequence) ? 1 1 replyShare MANSI_SOMANI commented Oct 24, 2022 reply Follow flag I think in question, Q op of JK ff is asked so bit sequence of Qjk is the ans whch isn't in ur ans but anyone can chk it from above answers we r gettign string of tht only 0 0 replyShare Saransh Maurya commented Dec 28, 2024 reply Follow flag this is good answer 0 0 replyShare Please log in or register to add a comment.
21 21 votes D QD QJK J K Q+JK 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 1 1 Answer = A = 01101101.... amarVashishth answered Oct 8, 2015 • edited Nov 19, 2015 by amarVashishth amarVashishth comment Share Follow 0 reply Please log in or register to add a comment.
11 11 votes Bit sequence is 0110110 Arnabi answered Jan 27, 2018 Arnabi comment Share Follow 0 reply Please log in or register to add a comment.
5 5 votes $Q_{1}^+ =\mathbf{D}=Q_2, \ Q_{2}^+ = \mathbf{JQ_2'+K'Q_2}= Q_1Q_2'+Q_1'Q_2=Q_1\oplus Q_2$ $$\begin{array}{|c|c|c|c|} \hline \bf{Q_1} & \bf {Q_2}& \bf {Q_1^+=Q_2} & \bf{Q_2^+=Q_1\oplus Q_2 }\\\hline1&0&0&1\\ 0&1&1&1\\1&1&1&0\\ 0&0&0&0\\\hline\end{array}$$ $Q_1$ $Q_2$ $:10\rightarrow01\rightarrow11\rightarrow10$ Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop $011011011....$ Correct Answer (A) KUSHAGRA गुप्ता answered Jul 22, 2020 KUSHAGRA गुप्ता comment Share Follow 0 reply Please log in or register to add a comment.
3 3 votes Caption Answer is A...... Sankha Narayan Bose answered Aug 17, 2018 Sankha Narayan Bose comment Share Follow 0 reply Please log in or register to add a comment.