• edited by
11,496 views
28 28 votes

For the synchronous counter shown in Fig$.3,$ write the truth table of $Q_{0}, Q_{1}$, and $Q_{2}$ after each pulse, starting from $Q_{0}=Q_{1}=Q_{2}=0$ and determine the counting sequence and also the modulus of the counter.

8 Answers

Best answer
32 32 votes

$$\begin{array}{|ccc|ccc|} \hline \textbf{$Q_0$} & \textbf {$Q_1$} &\textbf {$Q_2$} & \textbf {$Q_{0N}$} & \textbf{$Q_{1N }$}&\textbf{$Q_{2N}$} \\\hline \text{0}& \text{0} & \text{0}  & \text{0} & \text{0} &\text{1}\\\hline \text{0}& \text{0} & \text{1}  & \text{1} & \text{1} &\text{0}\\\hline \text{0}& \text{1} & \text{0}  & \text{1} & \text{0} &\text{0} \\\hline\text{0}& \text{1} & \text{1}  & \text{1} & \text{0} &\text{0} \\\hline\text{1}& \text{0} & \text{0}  & \text{0} & \text{0} &\text{0} \\\hline \text{1}& \text{0} & \text{1}  & \text{0} & \text{1} &\text{0} \\\hline \text{1}& \text{1} & \text{0}  & \text{0} & \text{1} &\text{0} \\\hline \text{1}& \text{1} & \text{1}  & \text{0} & \text{1} &\text{0} \\\hline \end{array}$$
$Q_{0N} = Q_0 \implies J_0 =  Q_1 + Q_2, K_0 = 1$

$Q_{1N} = Q_1 \implies J_1 =   Q_2, K_1 = \bar{Q_0}$

$Q_{2N} = Q_2 \implies J_2 =  \bar{Q_1}.\bar{Q_0}, K_2 = 1$

$$0 - 1 - 6 - 2- 4-0$$

So, MOD $5$ counter.

• edited by
10 10 votes
${\begin{array}{|c|c|c|}\hline
\bf{Q_0}&    \bf{Q_1}&  \bf{Q_2} \\\hline
0&0&0\\ 0&0&1 \\    1&1&0  \\   0&1&0\\   1&0&0  \\   0&0&0 \\ \hline
\end{array}}$

Counting sequence: $ 0-1-6-2-4$

As there are $5$ different states, so $5$ modulus
• edited by
0 0 votes

here if we want to solve such type of question then just  write q0 q1 q2 and also like input as previous output expression and just look at previous state and see how input are becoming for next state. like if  you see here if you want to make easy further then  we can make q0 q1 q3 as postion 0 1 2 now only try to identify  from which previous state postiion output coming to the next state

 

Position:
Show:

Related questions

25 25 votes
4 answers 4 answers
7.0k
7.0k views
Arjun asked Sep 22, 2015
6,996 views
Design a $3$-bit counter using D-flip flops such that not more than one flip-flop changes state between any two consecutive states.
60 60 votes
5 answers 5 answers
35.2k
35.2k views
ibia asked Nov 14, 2015
35,209 views
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $...
32 32 votes
2 answers 2 answers
10.7k
10.7k views
Misbah Ghaya asked Nov 19, 2016
10,740 views
The number of rooted binary trees with $n$ nodes is,Equal to the number of ways of multiplying $(n+1)$ matrices.Equal to the number of ways of arranging $n$ out of $2 n$ ...
9 9 votes
3 3 answers
1.9k
1.9k views
gatecse asked Feb 23
1,896 views
Consider a $2$-bit saturating up/down counter that performs the saturating up count when the input $P$ is $0$, and the saturating down count when $P$ is $1$. The Next Sta...