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Questions by someshawasthi
0
votes
1
answer
21
cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and acc...
374
views
asked
Nov 17, 2022
CO and Architecture
cache-memory
clock-cycles
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0
votes
0
answers
22
cache memory
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on this machine using a split cache of 32KB, obtained a 85% bit rate, 3ns bit time and 21ns miss penalty the execution time for the cache is ___ (μsec)
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on...
296
views
asked
Nov 16, 2022
CO and Architecture
co-and-architecture
cache-memory
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0
votes
1
answer
23
instruction-format
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then how many two instructions are possible at maximum?
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then ho...
545
views
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
instruction-format
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0
votes
1
answer
24
control signal
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
28 control signal to each micro operation has 2 control signal active at a time. Find minimum no. of bits need for control field.
241
views
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
control-unit
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0
votes
1
answer
25
SelfDoubt
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
360
views
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
self-doubt
machine-instruction
clock-cycles
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