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Questions by tvkkk
1
votes
1
answer
1
Admission Interviews
People who attended IISc CDS MTech admission interviews on 18th April 2017, can you please share your experience?
People who attended IISc CDS MTech admission interviews on 18th April 2017, can you please share your experience?
1.2k
views
asked
Apr 20, 2017
Interview Questions
iisc-interview
cds
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1
votes
2
answers
2
Is Sahni Horowitz book sufficient for Algorithms?
I know the textbook recommended for Algorithms is CLRS. However, I found it too much to digest. I instead bought the book by Horowitz and Sahni- Fundamentals of Computer Algorithms. Is this book sufficent for GATE?
I know the textbook recommended for Algorithms is CLRS. However, I found it too much to digest. I instead bought the book by Horowitz and Sahni- Fundamentals of Computer ...
1.3k
views
asked
Mar 31, 2017
Others
reference-book
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4
votes
0
answers
3
Ace Pre Gate 2017
All elements of a 2x2 matrix "A" can have values either 0 or 1. The probability that any element gets a value (0 or 1) is 1/2. If all elements of this matrix are chosen at random, what is the probability that the determinant of this matrix is positive?
All elements of a 2x2 matrix "A" can have values either 0 or 1. The probability that any element gets a value (0 or 1) is 1/2. If all elements of this matrix are chosen a...
2.3k
views
asked
Jan 16, 2017
Probability
probability
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1
votes
0
answers
4
GATE TEST SERIES
Suppose Ethernet physical addresses are chosen at random ( using true randombits). The probability that on a 1024-host network, two addresses will be the same? A) 1.77 x 10^-9 B) 1.87 x 10^-9 C) 1.99 x 10^-9 D) 1.98 x 10^-8
Suppose Ethernet physical addresses are chosen at random ( using true randombits). The probability that on a 1024-host network, two addresses will be the same?A) 1.77 x 1...
482
views
asked
Oct 4, 2016
2
votes
1
answer
5
Ace Booklet
The schedule S: T1: Read(X); T2: Write(X); T2: Write(Y); T3: Write(Y); T1: Write(Y); T1: commit; T2: commit; T3: commit; is Recoverable or non-recoverable?
The schedule S:T1: Read(X); T2: Write(X);T2: Write(Y);T3: Write(Y);T1: Write(Y);T1: commit; T2: commit;T3: commit;is Recoverable or non-recoverable?
634
views
asked
Sep 16, 2016
0
votes
1
answer
6
Ace Test
A TCP sender chooses and initial sequence number as 1093 and sends 1460 bytes of data to the receiver. The receiver has an initial sequence number 391 and acknowledgs the data to sender. The ACK number sent by receiver is:_____ My Answer is 2553. But the solution key says it's 2554. Please let me know your answer.
A TCP sender chooses and initial sequence number as 1093 and sends 1460 bytes of data to the receiver. The receiver has an initial sequence number 391 and acknowledgs the...
556
views
asked
Sep 2, 2016
Computer Networks
computer-networks
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1
votes
1
answer
7
MadeEasy Test Series: Operating System - File System
A file system with 512 GB disk uses a file descriptor with 16 direct block addresses, 1 indirect block address, 1 doubly indirect block address, 1 triple indirect block address. Size of each disk block is 256 bytes. And size of each disk block ... in GB) My answer is 0.008 GB In their solution, they say it's 8 GB, which I think is wrong.
A file system with 512 GB disk uses a file descriptor with 16 direct block addresses, 1 indirect block address, 1 doubly indirect block address, 1 triple indirect block a...
553
views
asked
Aug 29, 2016
Operating System
made-easy-test-series
operating-system
file-system
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2
votes
1
answer
8
General doubt
For incrementing or decrementing the value of Program Counter (PC), is switching to Kernel mode required?
For incrementing or decrementing the value of Program Counter (PC), is switching to Kernel mode required?
315
views
asked
Aug 29, 2016
CO and Architecture
co-and-architecture
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1
votes
2
answers
9
Coaching class booklet problem
In an instruction pipeline of 10 ns clock, the memory instruction takes 2 stalls while branch related instruction takes 3 stalls. If the frequency of memory related and branch instructions is 20% and 30% respectively. What is the average time taken by an instruction? a) 11.3 ns b) 13 ns c) 23 ns d) 13.3 ns
In an instruction pipeline of 10 ns clock, the memory instruction takes 2 stalls while branch related instruction takes 3 stalls. If the frequency of memory related and b...
428
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asked
Aug 27, 2016
CO and Architecture
pipelining
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0
votes
1
answer
10
General question related to the CPU
What is the difference between CPU clock cycle and CPU frequency? What is the relation between them?
What is the difference between CPU clock cycle and CPU frequency?What is the relation between them?
442
views
asked
Jul 3, 2016
0
votes
1
answer
11
General doubt
What is the difference between CPU frequency and Clock Cycle? What is the relation between them?
What is the difference between CPU frequency and Clock Cycle? What is the relation between them?
322
views
asked
Jul 3, 2016
0
votes
1
answer
12
What is the Network ID of 230.100.123.70 ?
3.6k
views
asked
Jun 22, 2016
Email or Username
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