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Doubt in pipelining

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  • I1: L R0, loc 1; R0 <= M[loc1]
  • I2: A R0, R0; R0 <= R0 +R0

       WB of I1  and ID stage of I2....should be overlapping or not?

How to consider this case...as in gate previous questions answers are changing according to the given options? 

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