Test by Bikram | Mock GATE | Test 1 | Question: 37

Question

A pulse train with a frequency of $1$ $MHz$ is counted using a modulo $1024$ ripple counter built with $J-K$ flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is:

• A. $10 \: nsec$
• B. $100 \: nsec$
• C. $1000 \: nsec$
• D. $100 \: microsec$

Comments

Explain this

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need explanation @Bikram sir

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https://gateoverflow.in/86736/test-by-bikram-2017-digital-design-set-2-20?show=329770#a329770

Answer 1

Frequency = 1 mega hertz so f = 1 MHz

so let the number of bits in the counter is n , 

1024 = 2ⁿ  so n = 10 

f = (1/ n * T_d ) [ T_d is propagation delay ] 

= > T_d = 1/nf

= 1/ ( 10 * 1 * 10⁶ )

= 100 * 10^-9 

= 100 nanoseconds  [ as  1 nano sec = 10⁻⁹  second ] 

hence T_d = 100ns .

Comments

sir can you explain it in words? the formula?

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@sheshang  and @uddipto

maximum clock frequency = 1/ minimum clock period 

Minimum clock period = number of bits in the counter  * Propagation delay

where number of bits in the counter is n  and T_d is propagation delay, now calculate propagation delay in this equation.

Maximum Clock Frequency. The clock frequency for a synchronous sequential circuit  ( j-k is an example of this type) is limited by the timing parameters of its flip-flops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency.

http://electronics.stackexchange.com/questions/221727/maximum-clock-frequency-for-a-sequential-circuit

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does this logic has to do something with toggling and race condition??

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this  concept is based on J-K flip flops so this logic have some relation with toggle and race condition.

Answer 2

 The time period produced by 1MHZ signal should compensate the maximum delay produced by all the flip flops.

As it is a ripple counter the maximum delay produced would be by the last flip-flop , = 10*Td.

therefore  1/10^6 = 10*Td.

Thus Td =100 ns 

Answer 3

No of bits in ripple counter 1024 = 2^10

n = 10  bits

Max permissible propagation delay  (Tp)= 1/n*frequency

                                                                 = 1/10*10^6

                                                                 = 10^2/10^6 * 10^2  [Asked in nano seconds]

                                                                =100 * 10^-9  ==> 100 nanoseconds