Log In
39 votes

Consider the Karnaugh map given below, where $X$ represents "don't care" and blank represents $0$.


Assume for all inputs $\left ( a,b,c,d \right )$, the respective complements $\left ( \bar{a}, \bar{b}, \bar{c}, \bar{d} \right )$ are also available. The above logic is implemented using $2$-input $\text{NOR}$ gates only. The minimum number of gates required is ____________ .

in Digital Logic
edited by

4 Answers

49 votes
Best answer

From K-map simplification we get the min-term as $CA'$. So We can simplyfy it for NOR gate expression

I.e. C' NOR $A = (C'+A)' = CA'$
Now complemented inputs are also given to us so, for $2$ input NOR gate we need only 1 NOR gate.

1 is correct answer .

edited by
can someone explain me with diagram how is the k-map reduced ? My answer is coming like : ca' + ac' which is by considering the two quad squares. Where am I wrong ? Why aren't we using the dont cares in first and fourth row ?

There isn't any requirement that don't cares MUST be used. If with the use of don't cares we can reduce the term size, only then a don't care need be used. 



a group cant consist of all dont cares

This function has same $SOP$ and $POS$ form - $c.a$'
For $SOP$ - $c.a'$ is treated as single term.
For $POS$ - $c.a'$ is treated as 2 terms each of which is composed of a single variable.
Don't we need one nor gate for inverting the input "C" as well? So 2 NOR gates should be required in my opinion.


No need NOR gate for inverting the input because  it's available in the question.

And one more thing, OR-AND realization is equal to NOR-NOR realization, so it's better we write Product of sum (POS) form.

My POS form is (a + c).(a' + c') and I'm not getting a'.c Can someone write its POS form?


can you show your solution?


I've done same mistake.

while computing POS, take don't care also to get the minimize POS form.

POS is A'C

17 votes

Answer : 1 Only

Here we should take note that all inputs (a,b,c,d) and their respective complements are available.

And now when we solve the K-map the we get minterms like :

- >    cb'a'+ cba' 

- >    ca'(b+b')

- >    ca' 

If we give input to a NOR gate as c' and a the output will be (c' + a )' =  ca'.

So, only 1 NOR gate is Required.


the expression which comes is only ca'  how did u get cb'a'+cba' ????

ca' is the minimized form .
Check my answer again.

@Bikram sir check pls

if  question is max number of nor gate :

 (c' + a )'

term with a single literal  (c' ) requires an inverter 

(instead using inverter we can also  use nor gate to get this ) in this case max nor gate =2


See this  Shivam Chauhan

in this case max nor will be 2

6 votes
Applying logic of k-map the simplified expression id ca'

now it is given that all inverted inputs are also available

so we can express ca' in terms of nor gate


so only 1 NOR gate required

1 is answer

ps: more editing will come
6 votes

The expression of $K-map$ is $c.\bar a$

so the expression should be in $POS$ form for $NOR$ gate 

$\overline{\overline{c.\bar a}} = \overline{\bar c + a} $

Now the expression is in $POS$ form

NOTE : $\bar a , \bar a , \bar c \text { is given so no need to use NOT gate for that}$



So only 1 $NOR$ gate required

edited by
What if the given K map itself is converted into a maxterms K map?

It should be $CA'$  brother, though the final answer won't change

@Sambhrant Maurya --> you will get $CA'$ itself as there are two octet of zero's .


@Hemanth_13 corrected


NOTE : a¯,a¯,c¯ is given so no need to use NOT gate for that

 It mean that if this was not given then minimum of nor gate required 2 ?
am i correct? 


OR-AND realization is equal to NOR - NOR realization, so we should write the POS(product of sum) form rather than the SOP(sum of product) form.

SOP: $f(b,a,d,c) = c \cdot a' $

POS: $f(b,a,d,c) = c\cdot a’ $

So, only one NOR gate is required.


 Pls can you Explain more after finding POS as (c + a'). How to apply this POS expression from NOR Gate?
I follow the same approach rather find POS not SOP.


Also In this Below question suggest me which approach to follow, as Convert min term SOP to POS or any other? 
What is the minimum number of 2-input NOR gates required to implement a 4-variable function function expressed in sum-of-minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available._________3.(Answer).

Actually the above method is more suitable when POS is given. But we got $a'+c$ which is sum term.

 $f(a,b,c,d) = \sum{(0,2,5,7,8,10,13,15)}$ Sum of Minterms(SOP)

$f(a,b,c,d) = \Pi{(0,2,5,7,8,10,13,15)}$ Product of Maxterms(POS)

Using $k-$map,we get

$f(a,b,c,d) = B'D'+BD$ (SOP)

$f(a,b,c,d) = (B'+D)\cdot(B+D')$ (POS)

Using the POS,we can easily make NOR gate.


Related questions

49 votes
10 answers
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ____________ bits.
asked Feb 14, 2017 in CO and Architecture Arjun 11.9k views
48 votes
2 answers
Consider the expression $(a-1) * (((b+c)/3)+d)$. Let $X$ be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which only load and store instructions can have memory operands and arithmetic instructions can have only register or immediate operands. ​​​​​​​The value of $X$ is _____________ .
asked Feb 14, 2017 in Compiler Design Arjun 11k views
67 votes
7 answers
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access ... $10$ times. The number of conflict misses experienced by the cache is _________ .
asked Feb 14, 2017 in CO and Architecture Arjun 19.8k views
35 votes
7 answers
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) respectively. A pipelined ... . The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________ .
asked Feb 14, 2017 in CO and Architecture khushtak 9.7k views