Instruction Pipelining

Question

Comments

How r they deciding stall delay as 4??

how to solve this question??

---

stall delay in execution of conditional instructions = (at which stage the branch address is available -1)

in this ques  branch address will be available in 5th stage , hence stall delay is 5.

Answer 1

when there is no branch...in pipeline manner all instreuctions wii come out every one cycle letter.

F

ID

O

E

W

F

ID

O

E

W

F

ID

O

E

W

SO TIME =.7*1*4 because clock cycle time is 4 ns.

now it is saying that cpu will not fetch new instruction in case of branch until last branch did not get complete, that means in branch case 

F

ID

O

E

W

F

ID

O

E

W

F

ID

O

E

W

SO after every 5 cycle we are getting our result so in this case .3*5*4 where  clock cycle time is 4 ns.

Answer 2

here for NON branch CPI=1 as per ideal condition 

for branch instructions CPI=5 as per statments ....so solution wll be  ...