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ISRO-DEC2017-71

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3 3 votes

A $32$-$bit$ adder is formed by cascading $4$-$bit$ CLA adder.The gate delays (latency)
for getting the sum bits is

  1. $16$
  2. $18$
  3. $17$
  4. $19$

4 Answers

7 7 votes

A 32 bit adder is formed by  cascading 4 bit CLA adder means 8 4 bit CLA are in one after another in sequence manner.In first,4 bit CLA circuit diagram as you can see that all data are present (A0 A1 A2 A3, B0 B1 B2 B3,C0 also) so for C4 it will take 3 cycles and Sum bits(S0 S1 S2 S3) take 1 more cycles. In this extra 1 cycles C4 will move to next CLA circuit and  make output C5 in 5 cycles and so on.So ,total gate delays=(1st +2nd+3rd+4th+5th+6th+7th+8th)=(3+2+2+2+2+2+2+3)=18 cycles.

If anyone have any doubt please ask me.

1 1 vote

​​​​​​8 four bit CLA are needed to create a 32 bit Adder 

P & G Generator  will take 1 gate delay (as EXOR and AND will operate in parallel) 

Carry generator will take 2 Gate delays (All AND in parallel (1)+All ORs in Parallel(1)=2)

C4 will be available to next CLA and next CLA will Take 2 gate delays also . During same time Sum Generator of first will calculate sums not taking any extra time 

same thing will happen for all 8 carry generators 2*8=16 .During the same time 7 Sum generators will calculate sum without taking extra time as all are working in parallel

Sum generator of last CLA will take 1 gate delay (all EX-or in parallel)

total 1+2*8+1=18

Answer option B

 

0 0 votes
4 bits CLA are cascaded means the bits are as follows

A0 A1 A2 A3| A4 A5 A6 A7 ... | A28 A29 A30 A31

B0 B1 B2 B3| B4 B5 B6 B7 ... | B28 B29 B30 B31

So we require 4 four-bit CLA in cascading manner to be 8.

 

Now for first CLA

C3: G2 + P2G1 + P2P1G0 + P2P1P0C0

Firstly we need G's and P's

Gi : ai AND bi

Pi : ai EXOR bi

Both take one delta time ( nothing given about delay time so assume to be delta for every gate )

Now, also the fan in for the AND and OR gate are also not given so we will take unlimited Fan In.

Therefore for AND and OR we gate 2 deltas.

 

This C3 will be passed to next CLA and it will also take the same time 2 delta delays.

For 8 CLA we get 2*8 : 16 deltas.

So we get C31 after 16 deltas

 

Now, for getting the final S31 bit:

we need P31 EXOR C31

For P31 we use one EXOR : 1 delta delay

And final EXOR with C31 also get 1 delta delay

 

 

Therefore, total delay is : 16 + 1 + 1 : 18 delta delays.
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