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20 votes
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Consider the following processor design characteristics:

  1. Register-to-register arithmetic operations only
  2. Fixed-length instruction format
  3. Hardwired control unit

Which of the characteristics above  are used in the design of a RISC processor?

  1. I and II only
  2. II and III only
  3. I and III only
  4. I, II and III
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4 Comments

  1. Register-to-register arithmetic operations only

Some people are thinking this statement is wrong. But notice keyword arithmetic.

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register to register can happen for logic/shift operations also, right ?
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@Shaik Masthan

Sir, except load/store all the other operations in RISC will be  reg-to-reg only right?

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7 Answers

29 votes
29 votes
Best answer

(D) All of these 

Hardwired control units are implemented through use of combinational logic units, featuring a finite number of gates that can generate specific results based on the instructions that were used to invoke those responses. Their design uses a fixed architecture—it requires changes in the wiring if the instruction set is modified or changed. This architecture is preferred in reduced instruction set computers (RISC) as they use a simpler instruction set.


Instructions length cannot vary in RISC usually it's $32$ bit. For CISC it can be between $16$ to $64$ bits. 

The hardwired control unit is used when instructions are fixed. 

Register to register operations is always possible in RISC. CISC can have memory to memory instructions also. 

References:

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4 Comments

@Akhilesh
 Some RISC instructions allow you to specify a signed constant, or “immediate” value, for the second source instead of a register.
RISC is still considered a load/store architecture, because arithmetic operands cannot be from arbitrary memory locations. They must either be registers or constants that are embedded in the instruction.
See this: https://courses.cs.washington.edu/courses/cse378/07au/lectures/L1.pdf (Page 9)
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@habedo007
Hardwired control units are implemented through use of combinational logic units, featuring a finite number of gates that can generate specific results based on the instructions that were used to invoke those responses. Hardwired control units are generally faster than microprogrammed designs. Their design uses a fixed architecture—it requires changes in the wiring if the instruction set is modified or changed. This architecture is preferred in reduced instruction set computers (RISC) as they use a simpler instruction set
Source: https://en.wikipedia.org/wiki/Control_unit#Hardwired_control_unit
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@Akhilesh Singla

This question is directly taken from Morris Mano book.

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15 votes
15 votes

Answer is D

I collected information from multiple sources and created this table. If you find anything wrong, please tell in the comment section.

CISC Vs RISC

Sl.no:

Parameter/Feature

RISC

CISC

1

Abbreviation

Reduced Instruction Set Computer

Complex Instruction Set Computer

2

Clock Cycle Per Instruction (CPI)

1(except LOAD and STORE)

Multiple

3

Average Clock Cycle Per Instruction (CPI)

1.5

2 to 15

4

Instruction Format

Fixed(usually 32 bits)

Varies

5

Performance Optimization

Software-centric approach

Hardware-centric approach

6

Coding

More lines of Code

Simple

7

Code Expansion

Can be Problematic

Not a problem

8

Complexity

Lies in compiler

Lies in microprogram

9

Instruction Set

Has Primitive instructions

Has variety of different instructions

10

Complex Addressing Modes

Synthesized using the software

Already supports complex addressing modes

11

Register Sets

Multiple

Unique

12

Total Registers

More than 256

Typically 6 to 16

13

Register Operands Per Instructon

Upto 3

Upto 2

14

No Of Instructions

Less

More

15

Instructions Accesing Memory

Only LOAD and STORE

Almost all from same set

16

RAM Usage

Heavy use of RAM(can cause bottleneck if RAM is limited)

Comparatively more efficient

17

Hardware Design Focus

Hardwired control

Micro-programmed control

18

Pipelining

Very High

Rare

19

Instruction Decoding

Simple

Complex

20

Transistors Usage

For memory registers

For storing complex instructions

21

Computation Operands

Register and Immediate only

Memory operands allowed

22

Disk Space

Space is saved

Space is wasted

23

Stalling

Mostly reduced in processors

Processors often stall

24

Portability

Less portable for design errors

Significant portable for design errors

25

Calculation Speed

Fast

Slow

26

Design Time

Less

Long

27

Memory Unit

Absent(uses a separate hardware to implement instructions)

Present

28

External Memory For Calculation Purpose

Not required

Needed

29

General Purpose Registers

32 to 192 with split data cache for instruction cache

8 to 24 general purpose registers with a unified cache for instructions and data (recent designs use split caches)

30

Memory Size Of Program

More space

Less space

31

Interruption

Responds to interrupt only at the proper place in instruction execution

Responds to an interrupt only at the end of execution

32

Conditional Jump

Based on a bit anywhere in memory

Based on status register bit

33

Instruction Format

Field Placement Varies

Regular Consistent placement of fields

34

 

Register to register: "LOAD" and "STORE" incorporated in instructions

Memory-to-memory: "LOAD" and "STORE" are independent instructions

35

Eg:

A = A * B; <<======this is C statement

LOAD R1, A          <<<======this is assembly statement

LOAD R2, B          <<<======this is assembly statement

PROD A, B          <<<======this is assembly statement

STORE R3, A          <<<======this is assembly statement

MULT A,B <<<======this is assembly statement

36

Processors

Ideal for processors performing dedicated operations

Ideal for processors performing a variety of operations

37

Instruction Fetching Time

Mostly same time

Different

38

Operands Per Instruction

Fixed

Variable

39

Applications

High-end applications such as video processing, telecommunications and image processing

Low-end applications such as security systems, home automation, etc.

40

Example

Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC

System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 CPUs

 

4 Comments

Hope you know not every source is reliable.
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Whats the feature or parameter name for point 34 @Balaji Jegan

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Please elaborate point 5.
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8 votes
8 votes

RISC is the traditional load/store architecture. It needs all the operands to be loaded in the registers first, and then the computations can be performed on them. (In CISC you don't need to load an operand in a register, you can directly access it from the memory)

So, I is correct.

 

RISC uses fixed-length instructions, while CISC uses variable-length instructions. For this reason, decoding an instruction is easier in RISC than in CISC.

So, II is correct.

 

RISC is more software-centric, while CISC is more Hardware-centric, BUT that doesn't mean it is dichotomous. Both architectures still need both software and hardware facilities.
For hardware, RISC has a hardwired control unit; whereas CISC has a micro-programmed control unit.
Hardwired CU is one of the consequences of the fixed-length instructions.

So, III is correct

 

Option D

2 Comments

Among all the answers present, this one is the best and easy to understand…
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Best, as always :)
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7 votes
7 votes
All of these

Instructions length cannot vary in RISC usually it's 32 bit. For CISC it can be between 16 to 64 bits.

Hardwired control unit are useful when instructions are fixed.

Register to register operations are always possible in RISC. CISC can have memory to memory instructions also.

Ref: https://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/2000-01/risc/risccisc/

1 comment

Register to register operations are always possible in RISC but in question it is mentioned only right ??

are you sure ?

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Answer:

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