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GATE CSE 2011 | Question: 21

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71 71 votes

Consider a hypothetical processor with an instruction of type $\text{LW  R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ register $\text{R1}$. The effective address of the memory location is obtained by the addition of a constant $20$ and the contents of register $\text{R2}$. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

  1. Immediate addressing
  2. Register addressing
  3. Register Indirect Scaled Addressing
  4. Base Indexed Addressing
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6 Answers

Best answer
77 77 votes

The answer is (D).

Base Index Addressing, as the content of register $\text{R2}$ will serve as the index, and $20$ will be the Base address.

• edited by
58 58 votes

The answer has to be option D.

Reason:It is mentioned in the question that the constant value 20 is added to the contents of Register R2(the word "CONSTANT" has got a significance here).The base address is something that remains CONSTANT under normal circumstances.The content of R2 is added to 20(constant base address) to get the effective address and this process resembles the way how we access an element of an array randomly.As we know that accessing of array elements is best done using INDEXED ADDRESSING hence the answer.

6 6 votes

Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

"best reflects" doesn't imply that it must be exactly that implementation..

Keeping that in mind, and also that options A and B could not be the candidates,

Let's focus on  $option \; C$ and $option \; D$

There is no literature that I found on the so called Indirect Scaled addressing.. 

There's nothing called Indirect Scaled Addressing, There is only scaled Base addressing where the scale is the number of bytes per offset..

But if we assume it exists and is similar to the Base Indexed addressing, then we have two valid interpretations, where both are consistent..

$R_1 \leftarrow  (A+(R_0))$ or $R_1 \leftarrow (20+(R_2))$ Base Indexed addressing, where 20 is assumed to be the base address

$R_1 \leftarrow  ((R_2)+20)$ Indirect Scaled offset [Access the register, add scaled offset(20) and get the data from the memory location]

It's debatable if Indirect Scaled offset is really even a thing, but considering yet another fact that there's generally no use of offset in Register Addressing, we conclude the best answer is $option\;D$

3 3 votes

I can clarify the confusion between option $(C)$ and $(D)$.

If you are thinking Register Indirect Scaled Addressing, is just a made up thing, it's not . ARM has a register indirect indexed mode, with scaling.

 

In Indexed (base) addressing mode: an offset is added to the base/index register. 

But "with scaling":  a scaling operation is performed before the offset is added to the index/base register.

LDR R0, [R1, R2, LSL #2]    ; R0 = *(R1 + (R2 << 2))
LDR R0, [R1, -R2, ASR #1]   ; R0 = *(R1 - (R2 >> 1))  signed shift

This scaling operation is performed by what ARM calls the "barrel shifter".

It can perform arithemetic shift right (ASR), logical shift left (LSL), logical shift right (LSR), right rotate (ROR) and rotate right extened (RRX).

 

Now we can just generalize this.

 If for any hypothetical processor, the effective address of the operand is calculated by scaling the offset value by some factor, and then adding this offset to some index/base register. 

Then we are using the so called Register Indirect Scaled Addressing mode.

Considering this, option $ (D)$ is correct.

 

For extra context, if we are talking about ARM, then -

$LW \  R1, 20(R2)$, would be register indirect indexing with offset. 

  LDR R0, [R1, #imm]      ; R0 = *(R1 + imm)
  LDR R0, [R1, #-imm]     ; R0 = *(R1 - imm)

 

 

 

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1 1 vote
Ans: D

Index     X(Ri)    EA=[Ri]+X  

Where  x=displacement

So here R2 is Index or Base register and 20 is displacement
0 0 votes
LW R1 , 20(R2)

options A,B are anyway out of the context.

first of all in such writings 2 symbols directly means indirect , 1) @  2) (  );

2nd of all in base addressing or based indexed addressing we do not I REPEAT we do not use the base value like this.

i dont know if option C is correct or not..

but D can't be the answer...

in based indexed addressing we must use 2 registers... giving 20 directly is not fulfilling the rules.

*****Wikipedia*****

(Effective address = contents of specified base register + contents of specified index register)

 

*****geeksforgeeks*****

 

Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]
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