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Consider a hypothetical processor with an instruction of type $\text{LW  R1, 20(R2)}$, which during execution reads a $32-bit$ word from memory and stores it in a $32-bit$ register $\text{R1}$. The effective address of the memory location is obtained by the addition of a constant $20$ and the contents of register $\text{R2}$. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

  1. Immediate addressing
  2. Register addressing
  3. Register Indirect Scaled Addressing
  4. Base Indexed Addressing
in CO and Architecture
edited by
7.6k views
1
Answer can never be A or B.
1
Plz correct me if wrong:

"The reason it cannot be register mode is because it is reading the address from memory, while, in register mode, address is never read from memory"?
1
Index Mode

The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code. Index Mode is used to access an array whose elements are in successive memory locations. The content of the instruction code, represents the starting address of the array and the value of the index register, and the index value of the current element. By incrementing or decrementing index register different element of the array can be accessed.
0
Why is it not register addressing?
0
Why not option C ?
8

Some related additional information -->

After reading this question some terms are coming in my mind for calculating effective address -->

  1. Addressing mode for Data (Used in sequential control flow)  -
    1. Immediate AM(addressing mode)  # 
    2. Register AM 
    3. Direct AM []
    4. Indirect AM(Register indirect AM and Memory Indirect AM)  @ or ()
    5. Indexed AM -
      1. Base Indexed Addressing - Base address is available in the address field of the instruction and index value is fetched from Index reg.
      2. In some processor we have designated register for both Base and Index value. 
      3. Auto indexed AM( [Base reg] + Step Size)
        • Auto increment and Auto Decrement  
    6. Implied (or Implicit) AM. (Ex - CLC, STC etc.)
  2. Addressing mode for Instruction(Used in transfer of Control) - 
    1. PC Relative AM (For accessing within segment) PC $\leftarrow$ PC + IR[Address Field].
    2. Base register AM or Based AM(For accessing instruction outside of the current segment) PC $\leftarrow$ [Base Reg.] + IR[Address Field]

PS: If something is missing or not proper please notify. It will be really helpful.

0
why not register indirect?
0
@sushmita in register indirect we hold the effective address in the register here we calculate it with additional index here the register is only the base
0
same question appeared in ISRO 2017 dec..
1

Purple

It's not Register Addressing because we don't use Offset in Register Addressing.

0
option D) Base indexed addressing

5 Answers

43 votes
 
Best answer

Answer is (D).

Base Index Addressing, as the content of register $R2$ will serve as the index and $20$ will be the Base address.


edited by
1
why are we not considering c as there is additive scaling
28

Hope, this will help!

0
why not immediate mode?
9

Why not reasoning for the answer be like,

Answer: D.

Base index addressing, as the content of the register, R2 will serve as the BASE and 20 will be the INDEX.

4
@Hemant . By standard we assume that the constant in the address field represent then Base address  and the index register contains index value.
0
Isnt based indexed addressing mode required to use base registers (BX and BP) and index registers (SI and DI)? If yes, then how is this based indexed addressing mode? Is it just conceptual, like we should have some fixed base address and indexing offset?
2

@Arjun

sir, why not option C ?

i mean there is no significance to the word "SCALED" in Register indirect scaled Addressing ?

0
@smartmeet For indexed mode, It should have been [(index*scale) + startAddress]. Because "index*scale" itself gives you displacement.
0

@Shaik Masthan

Please let me know if this understanding is correct.

I think it is not C)Register Indirect Scaled Addressing, because we do not have any indirect memory/register accesses.

21 votes

The answer has to be option D.

Reason:It is mentioned in the question that the constant value 20 is added to the contents of Register R2(the word "CONSTANT" has got a significance here).The base address is something that remains CONSTANT under normal circumstances.The content of R2 is added to 20(constant base address) to get the effective address and this process resembles the way how we access an element of an array randomly.As we know that accessing of array elements is best done using INDEXED ADDRESSING hence the answer.

1
Very good
0 votes
LW R1 , 20(R2)

options A,B are anyway out of the context.

first of all in such writings 2 symbols directly means indirect , 1) @  2) (  );

2nd of all in base addressing or based indexed addressing we do not I REPEAT we do not use the base value like this.

i dont know if option C is correct or not..

but D can't be the answer...

in based indexed addressing we must use 2 registers... giving 20 directly is not fulfilling the rules.

*****Wikipedia*****

(Effective address = contents of specified base register + contents of specified index register)

 

*****geeksforgeeks*****

 

Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]
0 votes

Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

"best reflects" doesn't imply that it must be exactly that implementation..

Keeping that in mind, and also that options A and B could not be the candidates,

Let's focus on  $option \; C$ and $option \; D$

There is no literature that I found on the so called Indirect Scaled addressing.. 

There's nothing called Indirect Scaled Addressing, There is only scaled Base addressing where the scale is the number of bytes per offset..

But if we assume it exists and is similar to the Base Indexed addressing, then we have two valid interpretations, where both are consistent..

$R_1 \leftarrow  (A+(R_0))$ or $R_1 \leftarrow (20+(R_2))$ Base Indexed addressing, where 20 is assumed to be the base address

$R_1 \leftarrow  ((R_2)+20)$ Indirect Scaled offset [Access the register, add scaled offset(20) and get the data from the memory location]

It's debatable if Indirect Scaled offset is really even a thing, but considering yet another fact that there's generally no use of offset in Register Addressing, we conclude the best answer is $option\;D$

0
I am still not convinced by the answer, and really wish the question was little clearer..

After some time I felt it's pointless debating a vaguely defined theory question.

Anyone comes up with a better explaination, or If I am wrong anywhere, please comment
–1 vote
Ans: D

Index     X(Ri)    EA=[Ri]+X  

Where  x=displacement

So here R2 is Index or Base register and 20 is displacement
Answer:

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