0 0 votes Encode the instruction sub r1, r2, 3 (a) 00001 0 0001 0010 00 0000 0000 0000 0011 (b)00001 1 0001 0010 00 0000 0000 0000 0011 (c) 00011 1 0001 0010 00 0000 0000 0000 0111 (d)None of the above CO & Architecture + – BASANT KUMAR 829 views answer comment Share Follow Print See all 4 Comments 4 4 Comments reply Shaik Masthan commented Aug 17, 2018 reply Follow flag with out knowing the SUB instruction implement ( how many instructions are there in your Instruction Set Architecture and etc..), and how many registers you have.. we can't answer this type of questions 1 1 replyShare goxul commented Aug 17, 2018 reply Follow flag As @Shaik pointed it out, this is specific to the Instruction Set Architecture of the processor. Without knowing the opcodes for SUB and the memory location of R1 and R2, it is not possible. 0 0 replyShare BASANT KUMAR commented Aug 17, 2018 reply Follow flag in question only above information is given. 0 0 replyShare goxul commented Aug 17, 2018 reply Follow flag If that's the case, the question is incorrect. 0 0 replyShare Please log in or register to add a comment.
