Consider the following code :
Load R1,M
Load R2,N
CMP R1,R2
JGE END
Store [300],R2
END: Store [300],R1
Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF ,ID, OF, EX and WB stages. OF refers to operand fetch i.e register read of operand. Operand forwarding and static branch prediction with prediction not taken are considered. The IF, ID, OF and WB stages take 1 clock cycle each for all instructions. The EX stage takes 2 clock cycles for CMP instruction, and 1 clock cycle for all other instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.
