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Consider a CPU containing 2000 instructions, there are 80 misses In the $L_1$ cache and 40 misses In the $L_2$ cache. Assume the miss penalty from the $L_2$ cache to memory is 200 clock cycles, the hit time of $L_2$ cache Is 30 clock cycles, the hit time of $L_1$ cache Is 5 clock cycles and these are 1.8 memory references per instruction, then average stall per instruction Is  _________.
 

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1.8 memory references for 1 instruction

Therefore for 1 memory reference = 1 / 1.8 = 10/18 = 5 / 9.

For 2000 memory references = (2000)*(5/9)

no of stall cycles=miss in L1*miss penalty in L1+miss in L2*miss penalty in L2

= 80 * 30 + 40 *200 = 10400

So avg no. of stalls per instruction = 10400 / (2000)*(5/9) = 9.36
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Number of instruction = $2000$

Miss rate of $L_{1}$ cache= $80$ clock cycles

Miss rate of $L_{2}$ cache= $40$ clock cycles

Miss Penalty for $L_{2}$ cache to memory $=200$ clock cycles

Hit time of $L_{1}$  is $=5$ clock cycles

Hit time of $L_{2}$  is $=30$ clock cycles

Now, Total instruction execution time  $=$ $L_{1} $hit time+$L_{1} $ miss time * $L_{2}$ hit time+$L_{2} $ miss time * $L_{2}$ miss penulty

$=5+80\times 30+40\times 200$

$=10405$ clock cycle

 

Now, $1$ instruction has memory reference $1.8$ clock cycle

then  $2000$ instruction has memory reference $1.8\times 2000=3600$clock cycle

 

So, total time where stall is generated $10405-3600=6805$ clock cycles

Then Avg instruction time when stall is generated $=\frac{6805}{2000}=3.4025$

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rahul sharma 5 asked Nov 6, 2017
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What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer