Number of instruction = $2000$
Miss rate of $L_{1}$ cache= $80$ clock cycles
Miss rate of $L_{2}$ cache= $40$ clock cycles
Miss Penalty for $L_{2}$ cache to memory $=200$ clock cycles
Hit time of $L_{1}$ is $=5$ clock cycles
Hit time of $L_{2}$ is $=30$ clock cycles
Now, Total instruction execution time $=$ $L_{1} $hit time+$L_{1} $ miss time * $L_{2}$ hit time+$L_{2} $ miss time * $L_{2}$ miss penulty
$=5+80\times 30+40\times 200$
$=10405$ clock cycle
Now, $1$ instruction has memory reference $1.8$ clock cycle
then $2000$ instruction has memory reference $1.8\times 2000=3600$clock cycle
So, total time where stall is generated $10405-3600=6805$ clock cycles
Then Avg instruction time when stall is generated $=\frac{6805}{2000}=3.4025$