ME Test Series

Question

Consider a CPU containing 2000 instructions, there are 80 misses In the $L_1$ cache and 40 misses In the $L_2$ cache. Assume the miss penalty from the $L_2$ cache to memory is 200 clock cycles, the hit time of $L_2$ cache Is 30 clock cycles, the hit time of $L_1$ cache Is 5 clock cycles and these are 1.8 memory references per instruction, then average stall per instruction Is  _________.
 

Comments

I didn't understand the question but have done some vague calculations and got answer as 6 .

Is that correct?

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I am getting $5.2$.

total no of instruction = $2000$

1 instruction --------  $1.8 $ MR

2000 Instruction -----------  $3600 $ MR

Miss in $L_1 = \frac{80}{3600}$

Miss in $L_2 = \frac{40}{80}$

Stalls per Memory Reference = $\frac{80}{3600} * (30 + \frac{40}{80}*200)$

= $\frac{26}{9}$ stalls / memory reference.

Means 1 MR ----------  $\frac{26}{9}$ stalls

Since every instruction is taking $1.8$ MR thus:-

Stalls per instruction -------  $\frac{26}{9}*1.8$

Stalls per instruction = $5.2$ stalls

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Yes I got the same but rounded it

Answer 1

1.8 memory references for 1 instruction

Therefore for 1 memory reference = 1 / 1.8 = 10/18 = 5 / 9.

For 2000 memory references = (2000)*(5/9)

no of stall cycles=miss in L1*miss penalty in L1+miss in L2*miss penalty in L2

= 80 * 30 + 40 *200 = 10400

So avg no. of stalls per instruction = 10400 / (2000)*(5/9) = 9.36

Comments

@Shubhanshu That is actually the same, indirectly.

https://www.geeksforgeeks.org/computer-organization-basic-computer-instructions/

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@srestha Ma'am checkout this link

https://www.geeksforgeeks.org/computer-organization-basic-computer-instructions/

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@JEET

I still not got, why we need to multiply hit and miss by memory reference i.e. $\frac{1.8}{2000}$?

Answer 2

Number of instruction = $2000$

Miss rate of $L_{1}$ cache= $80$ clock cycles

Miss rate of $L_{2}$ cache= $40$ clock cycles

Miss Penalty for $L_{2}$ cache to memory $=200$ clock cycles

Hit time of $L_{1}$  is $=5$ clock cycles

Hit time of $L_{2}$  is $=30$ clock cycles

Now, Total instruction execution time  $=$ $L_{1} $hit time+$L_{1} $ miss time * $L_{2}$ hit time+$L_{2} $ miss time * $L_{2}$ miss penulty

$=5+80\times 30+40\times 200$

$=10405$ clock cycle

 

Now, $1$ instruction has memory reference $1.8$ clock cycle

then  $2000$ instruction has memory reference $1.8\times 2000=3600$clock cycle

 

So, total time where stall is generated $10405-3600=6805$ clock cycles

Then Avg instruction time when stall is generated $=\frac{6805}{2000}=3.4025$

Comments

 

This is the solution which is given , i don't know what they have done

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@Shadan Karim Sorry that I made a very silly mistake in my solution.

Anyway the given solution is correct as I am also getting exactly the same answer.

Please read my solution once. If you need to ask something then let me know.