pipeline cycles

Question

I think they calculated whole things wrong.. with operand forwarding answer is 9,but they drew wrong diagram..and without answer will be 14.as we can use id stage under wb stage. so answer shoyld be 5. @arjun sir.

Comments

sir the half cycle procedure is in risc pipeline only ,. and i think if not given we should use the normal conventions. What if the state matches RISc processor. sir u solve this one . i am comfortable with 17 non operant forwarding . but not with operand forwarding . i think it should be 11

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There are many questions answered in this topic and I have given many references also. 

https://gateoverflow.in/tag/pipeline

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@Bhagirathi RD and Write can be done immediately as both are to/from register files. But suppose take EX stage- We cannot know when this will be done. It might involve many functional units and their upper bound is nothing but the period given by clock frequency. So, we cannot do clock split here. Same for MEM stage- we cannot do this immediately as we need data to arrive from/to memory.

Answer 1

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