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The instruction $LDA$ $FF0$ (machine code of $LDA$ is $5$) is stored in location $7F0$. The contents in memory location $FF0$  are loaded into accumulator.  After its execution, accumulator stores value $8$. The figure below shows a snapshot of the registers and their contents.

Immediately after the fetch cycle of the $1^{st}$ instruction ($LDA$ $FF0$), the values in $MAR$,  $IR$ and $MBR$ are:

 

  1. $MAR = FF0$,  $IR = 5FF0$, $MBR = 5FF0$
  2. $MAR = 7F0$,   $IR = 5FF0$, $MBR = 0008$
  3. $MAR = 7F0$,   $IR = 5FF0$, $MBR = 5FF0$
  4. $MAR = FF1$, $IR = 5FF0$, $MBR = 7F0$
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Step 1: PC will send the address of the instruction to the MAR

So MAR will contain the address of the instruction 5FF0 i.e 7F0

Now After the instruction is fetched,

Step 2: The result of memory access will be provided to MBR through system BUS, i.e the Instruction Itself

MBR contains 5FF0

Step 3: And further the contents of MBR will be provided to IR(Instruction Register) to store the instruction for the further decoding phase
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