1 1 vote The instruction $LDA$ $FF0$ (machine code of $LDA$ is $5$) is stored in location $7F0$. The contents in memory location $FF0$ are loaded into accumulator. After its execution, accumulator stores value $8$. The figure below shows a snapshot of the registers and their contents. Immediately after the fetch cycle of the $1^{st}$ instruction ($LDA$ $FF0$), the values in $MAR$, $IR$ and $MBR$ are: $MAR = FF0$, $IR = 5FF0$, $MBR = 5FF0$ $MAR = 7F0$, $IR = 5FF0$, $MBR = 0008$ $MAR = 7F0$, $IR = 5FF0$, $MBR = 5FF0$ $MAR = FF1$, $IR = 5FF0$, $MBR = 7F0$ CO & Architecture co-and-architecture nptel-quiz instruction-execution + – Yaman Sahu 973 views answer comment Share Follow Print See all 2 Comments 2 2 Comments reply Aashay kaurav commented Oct 7, 2021 reply Follow flag Option (B) ?? 0 0 replyShare Yaman Sahu commented Oct 7, 2021 reply Follow flag No answer is c src: Question 10 1 1 replyShare Please log in or register to add a comment.
Best answer 2 2 votes Step 1: PC will send the address of the instruction to the MAR So MAR will contain the address of the instruction 5FF0 i.e 7F0 Now After the instruction is fetched, Step 2: The result of memory access will be provided to MBR through system BUS, i.e the Instruction Itself MBR contains 5FF0 Step 3: And further the contents of MBR will be provided to IR(Instruction Register) to store the instruction for the further decoding phase Codered03 answered Oct 7, 2021 • edited Oct 10, 2021 by Codered03 Codered03 comment Share Follow 0 reply Please log in or register to add a comment.