Doubt regarding pipeline

Question

Hi, I have a question like how Load/Store operation behave in pipelining, with or without operand forwarding ?

Comments

@Nihal Singh

Without operand forwarding ..

Operand forwarding (or data forwarding) is an optimization in pipelined CPUs to limit performance deficits which occur due to pipeline stalls.

A data hazard can lead to a pipeline stall when the current operation has to wait for the results of an earlier operation which has not yet finished.

The CPU control unit must implement logic to detect dependencies where operand forwarding makes sense.

A multiplexer can then be used to select the proper register or flip-flop to read the operand from...

 

1. http://www.mhhe.com/engcs/electrical/hamacher/5e/graphics/ch08_453-510.pdf 

 

2. https://gateoverflow.in/239588/operand-forwarding-doubt 

 

3. https://gateoverflow.in/102565/operand-forwarding-in-pipeline 

 

4. https://www.techtud.com/doubt/operand-forwarding

 

5. https://gateoverflow.in/32274/pipelining-without-operand-forwarding 

 

 

 

 

 

Answer 1

If operand is present is specified as memeory location the content of it is loaded to a register using load instruction.
the instruction stores data from a specified register to a specified memory location.

Suppose x, y and z are memory location and we want to add the content of location x and y and store the result in memory location z. We can achieve it in 4 instruction
Load R1, x
Load r2, y
Add R3,  R1, R2
Store R3,z

In case of without operand forwarding when instruction is not dependent. we can execute instruction 1 and 2 in parallel using pipelining why we need to run them sequentially,this will enhance effiiciency.

ex:Load R1,x,Load R2,y;

Where as in case of operand forwarding when instruction may or may not be dependent we can use the register

buffer.

Some Advance Pipelining GATE Questions  

 

Answer 2

Like  we have instruction

1 a=b +c;

2 c=b+a;

we can see 2 is dependent on so 

Without oprand forwarding→ we know that we have 5 stages(fetch,decode,oprand fecth,execute,write back)

as we can see 2 is dependent on so so only after write back stage of instruction 1 is not completed we can go to  2 instruction,so it will result in increasing number of stalls. this is known a data hazard.

Example a=1,b=2,c=3;

a=2+3;

c=2+1;

but a should be 5 accoring to instrution so we can execute the second instruion after the 1^st only.this is known a data hazard.

With oprand forwarding=in oprand forward if you know we have a register buffer which stores if store value in buffer just after execution and pass to next instruction so we doesn’t need to write back.it’s decrease number of stalls.

To save from data hazards with decrease number of stalls we use data hazard.

Hope this is clear!

 

Comments

In the above example,

Load R1,x write the data in R1 at 5th cycle.

Load R2,x write the data in R2 at 6th cycle.

Now in the 3rd ALU instruction, it need R1,R2 for ID in 4th cycle let's say. But it has to wait till the 6th cycle completion. In without operand forwarding.

And 5th cycle with operand forwarding, because we can get the data from memory stage to ID

 

Help me out here.

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Yeess, you are right what’s your question.

but we can get the data of  I2 in  I3 in 4th(ID) cycle, beacause we have buffer /latch  between every stage.

see below diagram

 

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I think taking from the latch is the operand forwarding. And in load/store module the EA calculated at the EX, and MA access the register. And then the latch in between MA and WB can be used to do the transfer.