GATE IT 2004 | Question: 49

Question

A CPU has only three instructions $I1, I2$ and $I3,$ which use the following signals in time steps $T1-T5$:

$I1 : T1$ : Ain, Bout, Cin
         $T2$ : PCout, Bin
         $T3$ : Zout, Ain
         $T4$ : Bin, Cout
         $T5$ : End

$I2 : T1$ : Cin, Bout, Din
        $T2$ : Aout, Bin
        $T3$ : Zout, Ain
        $T4$ : Bin, Cout
        $T5$ : End

$I3 : T1$ : Din, Aout
        $T2$ : Ain, Bout
        $T3$ : Zout, Ain
        $T4$ : Dout, Ain
        $T5$ : End

Which of the following logic functions will generate the hardwired control for the signal Ain ?

• A. $T1.I1 + T2.I3 + T4.I3 + T3$
• B. $(T1 + T2 + T3).I3 + T1.I1$
• C. $(T1 + T2 ).I1 + (T2 + T4).I3 + T3$
• D. $(T1 + T2 ).I2 + (T1 + T3).I1 + T3$

Comments

Best Explained, thank you!

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nice 1 kushagra

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I found the solution on Youtube (might be helpful for you).

https://www.youtube.com/watch?v=JAqsXO3B62g

Answer 1

We just have to see which all options give $1$ whenever $A_{in}$ is $1$ and $0$ otherwise. 

So, Ain is $1$ in $T3$ of $I1, I2$ and $I3$. Also during $T1$ of $I1$, and $T2$ and $T4$ of $I3$. So, answer will be 

$T1.I1 + T2.I3 + T4.I3 + T3.I1 + T3.I2 + T3.I3$

Since CPU is having only $3$ instructions, $T3.I1 + T3.I2 + T3.I3$ can be replaced with $T3$ (we don't need to see which instruction and $A_{in}$ will be activated in time step $3$ of all the instructions).

So, $T1.I1 + T2.I3 + T4.I3 + T3 $

The answer is Option (A). 

Comments

best answer thnx a lot

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please don't copy paste made easy solution please explain by your own.

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who is copying the answer and look before commenting such crap

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T1

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For anyone wondering about the concepts behind this, see page 426 of Hamacher 5th edition. They describe the generation of signal Zin, where it is said to be "asserted during time slot T1 for all instructions", so just T1 is written in the logic function. It's probably due to the way the logic circuit is designed (instruction decoder does not need to choose between instructions in time slot T1, the signal is active for all).

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@pritishc do you have soft copy of the book??

Answer 2

	T1	T2	T3	T4	T5
I1	Ain		Ain
I2			Ain
I3		Ain	Ain	Ain

 

 

Ain = T1.I1 + T2.I3 + (I1+I2+I3).T3 + T4.I3   WE KNOW -> [I1 + I2 + I3 = 1]

 

Ain = T1.I1 + T2.I3 + T3 + T4.I3

 

So, Option A) is the correct answer.

Answer 3

Step 1: Making Table for easier understanding
 

Instr. \ Timer	T1	T2	T3	T4	T5
I1	Ain , Bout , Cin	Pcout , Bin	Zout , Ain	Bin , Cout	End
I2	Cin , Bout , Din	Aout , Bin	Zout , Ain	Bin , Cout	End
I3	Din , Aout	Ain , Bout	Zout , Ain	Dout , Ain	End

 

Step 2: Checking where Ain is enabled in given CPU

i.e., writing minterms for Ain :

Ain = I1.T1 + I3.T2 + I1.T3 + I2.T3 + I3.T3 + I3.T4

      = I1.T1 + I3.T2 + (I1+I2+I3).T3 + I3.T4 

      = I1.T1 + I3.T2 + T3 + I3.T4   (Since, I1 + I2 + I3 = 1 i.e., Identity) 

Therefore Option (A) is correct.