GATE IT 2005 | Question: 44

Question

We have two designs $D1$ and $D2$ for a synchronous pipeline processor. $D1$ has $5$ pipeline stages with execution times of $3$ nsec, $2$ nsec, $4$ nsec, $2$ nsec and $3$ nsec while the design $D2$ has $8$ pipeline stages each with $2$ nsec execution time How much time can be saved using design $D2$ over design $D1$ for executing $100$ instructions?

• A. $214$ nsec
• B. $202$ nsec
• C. $86$ nsec
• D. $-200$ nsec

Comments

202 !!!

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https://www.geeksforgeeks.org/gate-gate-cs-2000-question-8/

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$D1:$

$1\times 5\times 4+99\times 1\times 4=20+396=416ns$

$D2:$

$1\times 8\times 2+99\times 1\times 2=16+198=214ns$

$Time-saved: 416-214=202ns$

Answer 1

$(B)$ is the correct option for this question.

Execution time for Pipeline = $(K+n-1)*\text{execution_time}$   where $k$ = no of stages in pipeline, $n$ = no of instructions
Execution time = $\max$(all stages execution time)

$D_1 = (5+100-1)*4 = 416$

$D_2 = (8+100-1)*2 = 214$

Time saved using $D_2 = 416-214  =202$

Comments

just one thing 

in D1 it`s calculating like this for 1st instruction 5*4ns and remaining 99 instruction 4ns but 

why is it not like this for 1st instruction it should be (3+2+4+2+3)=14ns and remaining 99 instruction 4ns ???

plz explain 

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Nopes. because once pipelined we have to give same time for all pipeline stages as "synchronous" is mentioned in question. So, first instruction also takes 4 + 4 + 4 + 4 + 4 = 20ns and in every next 4ns another instruction finishes.

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D2 IS SYNCHRONOUS BUT D1 ISNT THATS WHY ITS HAS DIFF DIFFERENT EXECUTION TIME  .

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Both needs to be after pipelining:

"two designs D1 and D2 for a synchronous pipeline processor"

Otherwise, pipeline design will be incredibly complex. Input to one stage is waiting for output from previous stage- so there must be a synchronization. 

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The thing is after pipeining, all stages in D1 (not just stage 3) takes 4ns.

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@Arjun sir If it were not specified for both pipeline to be synchronous then do we calculate the time for first instruction using individual stage delays?

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The thing is after pipeining, all stages in D1 (not just stage 3) takes 4ns.

Arjun Sir, then what is the use of giving different times for each stage?

I mean if all have to be taken the same then there is no real use of giving different times for various stages in the question.

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If your doubt is cleared then please let me know the reason too. What I believe is if there are synchronous transfer / constant clocking rate terms are used then we need to use max(d1, d2, d3) where d1, d2, and d3 is the delay of stages S1, S2, S3 because then we need to have constant transfer for all the stages. And if those above-mentioned terms aren’t used then consider time for each stage of instruction, then using summation and the required formula we can easily calculate as we have done in this problem. If I am wrong then please correct me.

Answer 2

Execution time for pipeline = (K + n - 1 ) $\times$ Tp

Where n = number of instruction , K = number of stages Tp =  pipelene time

For D1: Pipeline time = max(3,2,4,2,3) = 4nsec

For D1: Pipeline time = max(2,2,2,2,2,2,2,2) = 2nsec

Execution time for pipeline D1 = (5 + 100 - 1 ) $\times$ 4nseec = 416nsec

​​​​​​​Execution time for pipeline D2 = (8 + 100 - 1 ) $\times$ 2nseec = 214nsec

Time saved = D1- D2 = 416- 208 = 202

Answer 3

Total execution time = (k + n – 1) * maximum clock cycle

Where k = total number of stages and n = total number of instructions

 

For D1 :

Total execution time = (5 + 100 – 1) * 4 = 416

 

For D2 :

k = 8 and n = 100

Total execution time = (8 + 100 – 1) * 2 = 214

 

Thus, time saved using D2 over D1 = 416 – 214 =202.
option (B) is correct one